ISBN: 3-540-66483-1
TITLE: Dependable Computing - EDDC-3
AUTHOR: Hlavicka, Jan; Maehle, Erik; Pataricza, Andras (Eds.)
TOC:

Keynote Speech
Reliable and Secure Operation of Smart Cards 3
H.H. Henn, IBM Germany, Bblingen, Germany
Session 1: Dependability Modelling
Chair: Jean-Claude Laprie, LAAS-CNRS, Toulouse, France
Dependability Modelling and Sensitivity Analysis of Scheduled Maintenance Systems 7
A. Bondavalli, I. Mura (CNUCE/CNR, Pisa, Italy), K.S. Trivedi (Duke University, Durham, USA)
Evaluation of Video Communication over Packet Switching Networks 24
K. Heidtmann (University of Hamburg, Germany)
Dependability Evaluation of a Distributed Shared Memory Multiprocessor System 42
M. Rabah, K. Kanoun (LAAS-CNRS, Toulouse, France)
Session 2a: Panel
Moderator: Fevzi Belli, University of Paderborn, Germany
Software Reliability Engineering  Risk Management for the New Millenium 63
F. Belli (University of Paderborn, Germany)
Session 2b: Fast Abstracts
Chair: Dimiter Avresky, Boston University, USA
List of Fast Abstracts 67
Session 3: Protocols
Chair: Istvn Majzik, Technical University of Budapest, Hungary
Muteness Failure Detectors: Specification and Implementation 71
A. Doudou (EPFL, Lausanne, Switzerland), B. Garbinato (United Bank of Switzerland, Zrich, Switzerland), R. Guerraoui, A. Schiper (EPFL, Lausanne, Switzerland)
A Fault Tolerant Clock Synchronization Algorithm for Systems with Low-Precision Oscillators 88
H. Lonn (Chalmers University of Technology, Gothenburg, Sweden)
Avoiding Malicious Byzantine Faults by a New Signature Generation Technique 106
K. Echtle (University of Essen, Germany)
An Experimental Evaluation of Coordinated Checkpointing in a Parallel Machine 124
L.M. Silva, J.G. Silva (Universidade de Coimbra, Portugal)
Session 4: Fault Injection 1
Chair: Janusz Sosnowski, Warsaw University of Technology, Poland
MAFALDA: Microkernel Assessment by Fault Injection and Design Aid 143
M. Rodrguez, F. Salles, J.-C. Fabre, J. Arlat (LAAS-CNRS, Toulouse, France)
Assessing Error Detection Coverage by Simulated Fault Injection 161
C. Constantinescu (Intel Corporation, Hillsboro, USA)
Considering Workload Input Variations in Error Coverage Estimation 171
P. Folkesson, J. Karlsson (Chalmers University of Technology, Gteborg, Sweden)
Session 5: Fault Injection 2
Chair: David Powell, LAAS-CNRS, Toulouse, France
Fault Injection into VHDL Models: Experimental Validation of a Fault-Tolerant Microcomputer System 191
D. Gil (Universidad Politcnica de Valencia, Spain), R. Martnez (Universitat de Valncia, Spain), J.V. Busquets, J.C. Baraza, P.J. Gil (Universidad Politcnica de Valencia, Spain)
Can Software Implemented Fault-Injection be Used on Real-Time Systems? 209
J.C. Cunha (Instituto Superior de Engenharia de Coimbra, Portugal), M.Z. Rela, J.G. Silva (Universidade de Coimbra, Portugal)
Session 6: Safety
Chair: Bernd Eschermann, ABB Power Automation AG, Baden, Switzerland
Integrated Safety in Flexible Manufacturing Systems 229
R. Apfeld (Berufsgenossenschaftliches Institut fr Arbeitssicherheit, St. Augustin, Germany), M. Umbreit (Fachausschu Eisen und Metall II, Mainz, Germany)
A Method for Implementing a Safety Control System Based on Its Separation into Safety-Related and Non-Safety-Related Parts 239
T. Shirai, M. Sakai, K. Futsuhara (Nippon Signal Co., Japan), M. Mukaidono (Meiji University, Japan)
Session 7: Hardware Testing
Chair: Raimund Ubar, Tallin Technical University, Estonia
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits 251
J.W. Greblicki, S.J. Piestrak (Wroclaw University of Technology, Poland)
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection
Networks 267
M. Bellos (University of Patras, Greece), D. Nikolos (University of Patras, and Computer Technology Institute, Patras, Greece), H.T. Vergos (Computer Technology Institute, Patras, Greece)
Diagnostic Model and Diagnosis Algorithm of a SIMD Computer 283
S. Chessa (CNR, Pisa, and University of Trento, Italy), B. Sallay, P. Maestrini (CNR, Pisa, Italy)
Session 8: Built-In Self-Test
Chair: Bernd Straube, Fraunhofer Gesellschaft, Institute for Integrated Circuits, Germany
Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata 303
O. Novk (Technical University Liberec, Czech Republic)
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits 321
T. Garbolino, A. Hlawiczka (Silesian Technical University of Gliwice, Poland)
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms 339
V.N. Yarmolik (Belorussian State University, Minsk, Belarus, and Bialystok University of Technology, Poland), I.V. Bykov (Belorussian State University, Minsk, Belarus), S. Hellebrand, H.-J. Wunderlich (University of Stuttgart, Germany)
Session 9: Networks and Distributed Systems
Chair: Gilles Muller, INRIA/IRISA, Rennes, France
Achieving Fault-Tolerant Ordered Broadcasts in CAN 351
J. Kaiser, M.A. Livani (University of Ulm, Germany)
Directional Gossip: Gossip in a Wide Area Network 364
M.-J. Lin (University of Texas at Austin, USA), K. Marzullo (University of California, San Diego, USA)
Efficient Reliable Real-Time Group Communication for Wireless Local Area Networks 380
M. Mock (GMD, St. Augustin, Germany), E. Nett (University of Magdeburg, Germany), S. Schemmer (GMD, St. Augustin, Germany)
Session 10: Software Testing and Self-Checking Chair: Luca Simoncini, CNUCE/CNR, Pisa, Italy
A Case Study in Statistical Testing of Reusable Concurrent Objects 401
H. Waeselynck, P. Thvenod-Fosse (LAAS-CNRS, Toulouse, France)
Fault-Detection by Result-Checking for the Eigenproblem 419
P. Prata (Universidade da Beira Interior, Covilh a, Portugal), J.G. Silva (Universidade de Coimbra, Portugal)
Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring 437
Y.-Y. Chen (Chung-Hua University, Hsin-Chu, Taiwan)
Author Index 455
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