ISBN: 3-540-41219-0
TITLE: Formal Methods in Computer Aided Design
AUTHOR: Hunt, Warren A. Jr.; Johnson, Steven D. (Eds.)
TOC:

Invited Talk 
Trends in Computing 1 
Mark E. Dean 
Invited Paper 
A Case Study in Formal Verification of Register-Transfer Logic with ACL2: 
The Floating Point Adder of the AMD Athlon (TM) Processor 3 
David M. Russinoff 
Contributed Papers 
An Algorithm for Strongly Connected Component Analysis in n log n 
Symbolic Steps 37 
Roderick Bloem, Harold N. Gabow, Fabio Somenzi 
Automated Refinement Checking for Asynchronous Processes 55 
Rajeev Alur, Radu Grosu, Bow-Yaw Wang 
Border-Block Triangular Form and Conjunction Schedule in Image 
Computation 73 
In-Ho Moon, Gary D. Hachtel, Fabio Somenzi 
B2M: A Semantic Based Tool for BLIF Hardware Descriptions 91 
David Basin, Stefan Friedrich, Sebastian Mdersheim 
Checking Safety Properties Using Induction and a SAT-Solver 108 
Mary Sheeran, Satnam Singh, Gunnar Stlmarck 
Combining Stream-Based and State-Based Verification Techniques 126 
Nancy A. Day, Mark D. Aagaard, Byron Cook 
A Comparative Study of Symbolic Algorithms for the Computation of Fair 
Cycles 143 
Kavita Ravi, Roderick Bloem, Fabio Somenzi 
Correctness of Pipelined Machines 161 
Panagiotis Manolios 
Do You Trust Your Model Checker? 179 
Wolfgang Reif, Jrgen Ruf, Gerhard Schellhorn, Tobias Vollmer 
Executable Protocol Specification in ESL 197 
Edmund M. Clarke, S. German, Y. Lu, Helmuth Veith, D. Wang 
Formal Verification of Floating Point Trigonometric Functions 217 
John Harrison 
Hardware Modeling Using Function Encapsulation 234 
Jun Sawada, Warren A. Hunt, Jr. 
A Methodology for the Formal Analysis of Asynchronous Micropipelines 246 
Antonio Cerone, George J. Milne 
A Methodology for Large-Scale Hardware Verification 263 
Mark D. Aagaard, Robert B. Jones, Thomas F. Melham, 
John W. O'Leary, Carl-Johan H. Seger 
Model Checking Synchronous Timing Diagrams 283 
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Kedar S. Namjoshi 
Model Reductions and a Case Study 299 
Jin Hou, Eduard Cerny 
Modeling and Parameters Synthesis for an Air Traffic Management System 316 
Adilson Luiz Bonifcio, Arnaldo Vieira Moura 
Monitor-Based Formal Specification of PCI 335 
Kanna Shimizu, David L. Dill, Alan J. Hu 
SAT-Based Image Computation with Application in Reachability Analysis 354 
Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta 
SAT-Based Verification without State Space Traversal 372 
Per Bjesse, Koen Claessen 
Scalable Distributed On-the-Fly Symbolic Model Checking 390 
Shoham Ben-David, Tamir Heyman, Orna Grumberg, Assaf Schuster 
The Semantics of Verilog Using Transition System Combinators 405 
Gordon J. Pace 
Sequential Equivalence Checking by Symbolic Simulation 423 
Gerd Ritter 
Speeding Up Image Computation by Using RTL Information 443 
Christoph Meinel, Christian Stangier 
Symbolic Checking of Signal-Transition Consistency for Verifying 
High-Level Designs 455 
Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara 
Symbolic Simulation with Approximate Values 470 
Chris Wilson, David L. Dill, Randal E. Bryant 
A Theory of Consistency for Modular Synchronous Systems 486 
Randal E. Bryant, Pankaj Chauhan, Edmund M. Clarke, Amit Goel 
Verifying Transaction Ordering Properties in Unbounded Bus Networks 
through Combined Deductive/Algorithmic Methods 505 
Michael Jones, Ganesh Gopalakrishnan 
Visualizing System Factorizations with Behavior Tables 520 
Alex Tsow, Steven D. Johnson 
Author Index 539 
END
