ISBN: 3-540-64976-X
TITLE: Architecture Design and Validation Methods
AUTHOR: Brger, Egon (Ed.)
TOC:

Modeling and Synthesis of Behavior, Control 
and Data Flow 1 
Raul Camposano, Andrew Seawright, Joseph Buck 
1 Introduction 1 
2 Behavioral Synthesis 3 
3 High-Level Control 15 
4 Data Flow 24 
5 Conclusion 42 
References 42 
Cell-based Logic Optimization 49 
Giovanni De Micheli 
1 Introduction 49 
2 Problem Formulation and Analysis 49 
3 Algorithms for Library Binding 52 
4 Boolean Matching 60 
5 Generalized Matching 78 
6 Conclusion 83 
References 84 
A Design Flow for Performance Planning: 
New Paradigms for Iteration Free Synthesis 89 
Ralph H.J.M. Otten 
1 Introduction 89 
2 Flow Components 92 
3 Layout Synthesis 99 
4 Placement Versus Floorplan Design 101 
5 Global Wires 115 
6 Wire Planning 122 
7 Gate Sizing 127 
8 Conclusions 137 
References 138 
Test and Testable Design 141 
Hans-Joachim Wunderlich 
1 Introduction 141 
2 Defect Analysis and Fault Modeling 143 
3 External Testing 155 
4 Self-Testable Systems-On-Chip 162 
References 185 
Machine Assisted Verification 191 
Hans Eveking 
1 Introduction 191 
2 Logic Verification 195 
3 Bit-Vector and Word-Level Verification 207 
4 Verification by Fixed-Point Calculations 211 
5 Verification Techniques for Bounded State Sequences 218 
6 Formally Correct Construction of Pipelined Systems 231 
References 238 
Models of Computation for System Design 243 
Luciano Lavagno, Alberto Sangiovanni-Vincentelli, 
and Ellen M. Sentovich 
1 Introduction 243 
2 MOCs: Basic Concepts and the Tagged Signal Model 248 
3 Common Models of Computation 261 
4 Codesign Finite State Machines 276 
5 Conclusions 289 
References 292 
Modular Design for the Java Virtual Machine Architecture 297 
Egon Brger and Wolfram Schulte 
1 Introduction 297 
2 The Trustful Virtual Machine 301 
3 The Defensive Virtual Machine 313 
4 The Diligent Virtual Machine 323 
5 The Dynamic Virtual Machine 334 
6 Related and Future Work 344 
7 The JVM Abstract State Machine 346 
References 356 
END
