library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity example is

    Port ( A : in std_logic;

           B : in std_logic;

           C : in std_logic;

           D : in std_logic;

           OUTPUT : out std_logic);

end entity example;

architecture Behavioural of example is

begin

OUTPUT <= not (((A or B) and C) and D);

end architecture Behavioural;