LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


ENTITY testbench IS
END testbench;


ARCHITECTURE behavior OF testbench IS 

          COMPONENT example
          PORT(
                  A, B, C, D : IN  std_logic;
                  OUTPUT :     OUT std_logic);
          END COMPONENT;

          SIGNAL A, B, C, D, OUTPUT :  std_logic;

BEGIN

uut: example PORT MAP(A => A, B => B, C => C, D => D, OUTPUT => OUTPUT);

testbench : PROCESS
BEGIN
             wait for  0 ns; A <= '0'; B <= '0'; C <= '0'; D <= '0';
 	   wait for 10 ns; A <= '0'; B <= '0'; C <= '0'; D <= '1';
	   wait for 10 ns; A <= '0'; B <= '0'; C <= '1'; D <= '0';
	   wait for 10 ns; A <= '0'; B <= '0'; C <= '1'; D <= '1';
	   wait for 10 ns; A <= '0'; B <= '1'; C <= '0'; D <= '0';
 	   wait for 10 ns; A <= '0'; B <= '1'; C <= '0'; D <= '1';
	   wait for 10 ns; A <= '0'; B <= '1'; C <= '1'; D <= '0';
	   wait for 10 ns; A <= '0'; B <= '1'; C <= '1'; D <= '1';
	   wait for 10 ns; A <= '1'; B <= '0'; C <= '0'; D <= '0';
 	   wait for 10 ns; A <= '1'; B <= '0'; C <= '0'; D <= '1';
	   wait for 10 ns; A <= '1'; B <= '0'; C <= '1'; D <= '0';
	   wait for 10 ns; A <= '1'; B <= '0'; C <= '1'; D <= '1';
	   wait for 10 ns; A <= '1'; B <= '1'; C <= '0'; D <= '0';
 	   wait for 10 ns; A <= '1'; B <= '1'; C <= '0'; D <= '1';
	   wait for 10 ns; A <= '1'; B <= '1'; C <= '1'; D <= '0';
	   wait for 10 ns; A <= '1'; B <= '1'; C <= '1'; D <= '1';
             wait for 10 ns;

END PROCESS testbench;

END;
