Design (gates_vhdl.vhd)

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-- VHDL description for combinational logic circuit.

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-- Library Definitions

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

LIBRARY COMPONENTS;

USE COMPONENTS.LOGIC.ALL;

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-- Entity Definition

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ENTITY gates_vhdl IS

   PORT ( A          :          IN          STD_LOGIC;

          B          :          IN          STD_LOGIC;

          C          :          IN          STD_LOGIC;

          Z          :          OUT          STD_LOGIC);

end gates_vhdl;

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-- Architecture Definition

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ARCHITECTURE SCHEMATIC OF gates_vhdl IS

   SIGNAL node1          :          STD_LOGIC;

   SIGNAL node2          :          STD_LOGIC;

   SIGNAL node3          :          STD_LOGIC;

   SIGNAL node4          :          STD_LOGIC;

   SIGNAL node5          :          STD_LOGIC;

   COMPONENT AND2

      PORT ( I0          :          IN          STD_LOGIC;

             I1          :          IN          STD_LOGIC;

             O          :          OUT          STD_LOGIC);

   END COMPONENT;

   COMPONENT INV

      PORT ( I          :          IN          STD_LOGIC;

             O          :          OUT          STD_LOGIC);

   END COMPONENT;

   COMPONENT OR3

      PORT ( I0          :          IN          STD_LOGIC;

             I1          :          IN          STD_LOGIC;

             I2          :          IN          STD_LOGIC;

             O          :          OUT          STD_LOGIC);

   END COMPONENT;

BEGIN

   I1 : AND2 PORT MAP (I0=>A, I1=>B, O=>node3);

   I2 : AND2 PORT MAP (I0=>node1, I1=>node2, O=>node4);

   I3 : AND2 PORT MAP (I0=>node2, I1=>B, O=>node5);

   I4 : INV  PORT MAP (I=>A, O=>node1);

   I5 : INV  PORT MAP (I=>C, O=>node2);

   I6 : OR3  PORT MAP (I0=>node3, I1=>node4, I2=>node5, O=>Z);

END SCHEMATIC;

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-- End of File

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Design Test Bench (test_gates_vhdl.vhd)

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-- VHDL Test Bench Created to simulate source file gates.vhd

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-- Library Definitions

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

LIBRARY COMPONENTS;

USE COMPONENTS.LOGIC.ALL;

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-- Entity Definition

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ENTITY testbench IS

END testbench;

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-- Architecture Definition

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ARCHITECTURE behavioral OF testbench IS

   COMPONENT gates_vhdl

   PORT( A          :          IN          STD_LOGIC;

          B          :          IN          STD_LOGIC;

          C          :          IN          STD_LOGIC;

          Z          :          OUT          STD_LOGIC);

   END COMPONENT;

   SIGNAL A          :          STD_LOGIC;

   SIGNAL B          :          STD_LOGIC;

   SIGNAL C          :          STD_LOGIC;

   SIGNAL Z          :          STD_LOGIC;

BEGIN

   UUT: gates_vhdl PORT MAP(

                    A => A,

                    B => B,

                    C => C,

                    Z => Z);

   test_stimulus : PROCESS

   BEGIN

      WAIT for 0 ns;   A <= '0'; B <='0'; C <= '0';

      WAIT for 100 ns; A <= '0'; B <='0'; C <= '1';

      WAIT for 100 ns; A <= '0'; B <='1'; C <= '0';

      WAIT for 100 ns; A <= '0'; B <='1'; C <= '1';

      WAIT for 100 ns; A <= '1'; B <='0'; C <= '0';

      WAIT for 100 ns; A <= '1'; B <='0'; C <= '1';

      WAIT for 100 ns; A <= '1'; B <='1'; C <= '0';

      WAIT for 100 ns; A <= '1'; B <='1'; C <= '1';

      WAIT for 100 ns;

   END PROCESS;

END;

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-- End of File

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