Design (encoder.vhd)

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-- VHDL model for a Priority Encoder

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-- Library Definitions

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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-- Entity Definition

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entity encoder is

    Port (A      :     in   std_logic_vector(7 downto 0);

          B      :     out  std_logic_vector(2 downto 0);

          Valid  :     out  std_logic);

end entity encoder;

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-- Architecture Definition

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architecture simple of encoder is

begin

  B <=    "000"            when            A = "00000001"  else

          "001"            when            A = "00000010"  else

          "010"            when            A = "00000100"  else

          "011"            when            A = "00001000"  else

          "100"            when            A = "00010000"  else

          "101"            when            A = "00100000"  else

          "110"            when            A = "01000000"  else

          "111"            when            A = "10000000"  else

          "000";

Valid <= '1'        when      (A = "00000001" or  A = "00000010"

                    or         A = "00000100" or  A = "00001000"

        or         A = "00010000" or  A = "00100000"

        or         A = "01000000" or  A = "10000000")

        else      '0';

end architecture simple;

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-- End of File

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Design Test Bench (test_encoder.vhd)

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-- VHDL Test Bench Created to simulate source file encoder.vhd

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-- Library Definitions

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

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-- Entity Definition

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ENTITY testbench IS

END testbench;

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-- Architecture Definition

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ARCHITECTURE behavior OF testbench IS

          COMPONENT encoder

          PORT(     a     : IN std_logic_vector(7 downto 0);         

                    b     : OUT std_logic_vector(2 downto 0);

                    valid : OUT std_logic);

          END COMPONENT;

          SIGNAL a      :  std_logic_vector(7 downto 0);

          SIGNAL b      :  std_logic_vector(2 downto 0);

          SIGNAL valid  :  std_logic;

BEGIN

uut: encoder PORT MAP(a => a, b => b, valid => valid);

   test_stimulus : PROCESS

   BEGIN

  -- Normal (expected) inputs

          wait for 0 ns;    a <= "00000001";

          wait for 100 ns;  a <= "00000010";

          wait for 100 ns;  a <= "00000100";

          wait for 100 ns;  a <= "00001000";

          wait for 100 ns;  a <= "00010000";

          wait for 100 ns;  a <= "00100000";

          wait for 100 ns;  a <= "01000000";

          wait for 100 ns;  a <= "10000000";

 -- Selected unexpected inputs

          wait for 100 ns;  a <= "00000000";

          wait for 100 ns;  a <= "00000011";

          wait for 100 ns;  a <= "00001100";

          wait for 100 ns;  a <= "00110000";

          wait for 100 ns;  a <= "11000000";

          wait for 100 ns;  a <= "11111111";

   END PROCESS;

END;

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-- End of File

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