Design (counter.vhd)

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-- VHDL description for 3-bit counter circuit.

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-- Library Definitions

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

LIBRARY COMPONENTS;

USE COMPONENTS.LOGIC.ALL;

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-- Entity Definition

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ENTITY counter IS

   PORT ( Clk        :          IN          STD_LOGIC;

          Reset      :          IN          STD_LOGIC;

          A          :          OUT         STD_LOGIC;

          B          :          OUT         STD_LOGIC;

          C          :          OUT         STD_LOGIC);

end counter;

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-- Architecture Definition

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ARCHITECTURE structural OF counter IS

   SIGNAL An          :          STD_LOGIC;

   SIGNAL Bn          :          STD_LOGIC;

   SIGNAL Cn          :          STD_LOGIC;

   SIGNAL Db          :          STD_LOGIC;

   SIGNAL Dc          :          STD_LOGIC;

   SIGNAL X1          :          STD_LOGIC;

   SIGNAL X2          :          STD_LOGIC;

   SIGNAL X3          :          STD_LOGIC;

   COMPONENT AND2

      PORT ( I0       :          IN          STD_LOGIC;

             I1       :          IN          STD_LOGIC;

             O        :          OUT          STD_LOGIC);

   END COMPONENT;

   COMPONENT AND3

      PORT ( I0       :          IN          STD_LOGIC;

             I1       :          IN          STD_LOGIC;

             I2       :          IN          STD_LOGIC;

             O        :          OUT          STD_LOGIC);

   END COMPONENT;

   COMPONENT DFF

      PORT ( C        :          IN          STD_LOGIC;

             CLR      :          IN          STD_LOGIC;

             D        :          IN          STD_LOGIC;

             Q        :          OUT          STD_LOGIC);

   END COMPONENT;

   COMPONENT INV

      PORT ( I        :          IN          STD_LOGIC;

             O        :          OUT          STD_LOGIC);

   END COMPONENT;

   COMPONENT OR3

      PORT ( I0       :          IN          STD_LOGIC;

             I1       :          IN          STD_LOGIC;

             I2       :          IN          STD_LOGIC;

             O        :          OUT          STD_LOGIC);

   END COMPONENT;

   COMPONENT XOR2

      PORT ( I0       :          IN          STD_LOGIC;

             I1       :          IN          STD_LOGIC;

             O        :          OUT          STD_LOGIC);

   END COMPONENT;

BEGIN

   I0 : AND2         PORT MAP (I0=>Cn, I1=>A, O=>X1);

   I1 : AND2         PORT MAP (I0=>Bn, I1=>A, O=>X2);

   I2 : AND3         PORT MAP (I0=>C, I1=>B, I2=>An, O=>X3);

   I3 : DFF          PORT MAP (C=>Clk, CLR=>Reset, D=>Db, Q=>B);

   I4 : DFF          PORT MAP (C=>Clk, CLR=>Reset, D=>An, Q=>A);

   I5 : DFF          PORT MAP (C=>Clk, CLR=>Reset, D=>Dc, Q=>C);

   I6 : INV          PORT MAP (I=>A, O=>An);

   I7 : INV          PORT MAP (I=>B, O=>Bn);

   I8 : INV          PORT MAP (I=>C, O=>Cn);

   I9 : OR3          PORT MAP (I0=>X1, I1=>X2, I2=>X3, O=>Dc);

   I10 : XOR2        PORT MAP (I0=>C, I1=>B, O=>Db);

END structural;

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-- End of File

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