Design (lfsr.vhd)

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-- VHDL description for 3-bit counter circuit.

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-- Library Definitions

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

LIBRARY COMPONENTS;

USE COMPONENTS.LOGIC.ALL;

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-- Entity Definition

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ENTITY lfsr IS

   PORT ( Clk         :          IN          STD_LOGIC;

          Reset       :          IN          STD_LOGIC;

          Qa          :          OUT          STD_LOGIC;

          Qb          :          OUT          STD_LOGIC;

          Qc          :          OUT          STD_LOGIC);

end lfsr;

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-- Architecture Definition

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ARCHITECTURE structural OF lfsr IS

   SIGNAL X1            :          STD_LOGIC;

   COMPONENT DFF

      PORT ( C          :          IN          STD_LOGIC;

             D          :          IN          STD_LOGIC;

             R          :          IN          STD_LOGIC;

             Q          :          OUT          STD_LOGIC);

   END COMPONENT;

   COMPONENT DFFs

      PORT ( C          :          IN          STD_LOGIC;

             D          :          IN          STD_LOGIC;

             S          :          IN          STD_LOGIC;

             Q          :          OUT          STD_LOGIC);

   END COMPONENT;

   COMPONENT XOR2

      PORT ( I0         :          IN          STD_LOGIC;

             I1         :          IN          STD_LOGIC;

             O          :          OUT          STD_LOGIC);

   END COMPONENT;

BEGIN

   I0 : DFF           PORT MAP (C=>Clk, D=>X1, R=>Reset, Q=>Qa);

   I1 : DFF           PORT MAP (C=>Clk, D=>Qa, R=>Reset, Q=>Qb);

   I2 : DFFs          PORT MAP (C=>Clk, D=>Qb, S=>Reset, Q=>Qc);

   I3 : XOR2          PORT MAP (I0=>Qb, I1=>Qc, O=>X1);

END structural;

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-- End of File

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