Design
(rom.vhd)
-----------------------------------------------------------------
--
VHDL model for a 4 x 8-bit ROM
-----------------------------------------------------------------
--
The model is a simple input-output value mapping. There are no
--
control signals and the output is defined to create a logic '0'
--
or '1' at all times. The output creates a RAMP signal which if
--
fed to an 8-bit DAC will create a coarse ramp output(voltage
--
or current).
-----------------------------------------------------------------
-----------------------------------------------------------------
--
Library Definitions
-----------------------------------------------------------------
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------
--
Entity Definition
-----------------------------------------------------------------
entity
ROM is
Port ( address :
in Integer range
0 to 15;
data :
out std_logic_vector(7
downto 0));
end
entity ROM;
-----------------------------------------------------------------
--
Architecture Definition
-----------------------------------------------------------------
architecture
Simple of ROM is
type
rom_array is array (0 to 15) of std_logic_vector(7 downto 0);
constant
ROM: rom_array := (
"00000000",
"00010000",
"00100000",
"00110000",
"01000000",
"01010000",
"01100000",
"01110000",
"10000000",
"10010000",
"10100000",
"10110000",
"11000000",
"11010000",
"11100000",
"11110000");
begin
data <= rom(address);
end
architecture Simple;
-----------------------------------------------------------------
--
End of File
-----------------------------------------------------------------
Design
Test Bench (test_rom.vhd)
-----------------------------------------------------------------
--
VHDL Test Bench Created to simulate source file ramp.vhd
-----------------------------------------------------------------
-----------------------------------------------------------------
--
Library Definitions
-----------------------------------------------------------------
LIBRARY
ieee;
USE
ieee.std_logic_1164.ALL;
USE
ieee.numeric_std.ALL;
-----------------------------------------------------------------
--
Entity Definition
-----------------------------------------------------------------
ENTITY
testbench IS
END
testbench;
-----------------------------------------------------------------
--
Architecture Definition
-----------------------------------------------------------------
ARCHITECTURE
behavior OF testbench IS
COMPONENT ROM
PORT(
address : IN Integer range 0 to 15;
data : OUT
std_logic_vector(7 downto 0));
END COMPONENT;
SIGNAL address : Integer
range 0 to 15;
SIGNAL data : std_logic_vector(7
downto 0);
BEGIN
uut: ROM PORT MAP(address => address, data => data);
test_stimulus
: PROCESS
BEGIN
wait for 0 ns; address
<= 0;
wait for 100 ns; address
<= 1;
wait for 100 ns; address
<= 2;
wait for 100 ns; address
<= 3;
wait for 100 ns; address
<= 4;
wait for 100 ns; address
<= 5;
wait for 100 ns; address
<= 6;
wait for 100 ns; address
<= 7;
wait
for 100 ns; address <= 8;
wait for 100 ns; address
<= 9;
wait for 100 ns; address
<= 10;
wait for 100 ns; address
<= 11;
wait for 100 ns; address
<= 12;
wait for 100 ns; address
<= 13;
wait for 100 ns; address
<= 14;
wait for 100 ns; address
<= 15;
wait for 100 ns;
END
PROCESS;
END;
-----------------------------------------------------------------
--
End of File
-----------------------------------------------------------------