Design (ram.vhd)

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-- VHDL description for 4x4 RAM circuit.

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-- Library Definitions

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

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-- Entity Definition

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entity ram is

    Port ( address           : in    Integer range 0 to 15;

           ce                : in    std_logic;

           we                : in    std_logic;

           oe                : in    std_logic;

           data              : inout std_logic_vector(7 downto 0));

end entity ram;

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-- Architecture Definition

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architecture simple of ram is

begin

memory:process(address, ce, we, oe) is

type ram_array is array (0 to 15) of std_logic_vector(7 downto 0);

variable mem: ram_array;

begin

data <= (others => 'Z');

          if (ce = '0') then

                    if (we = '0') then

                             mem(address) := data;

                    elsif (oe = '0') then

                             data <= mem(address);

                    end if;

          end if;

end process memory;

end architecture simple;

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-- End of File

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Design Test Bench (test_ram.vhd)

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-- VHDL Test Bench Created to simulate source file ram.vhd

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-- Library Definitions

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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

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-- Entity Definition

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ENTITY testbench IS

END testbench;

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-- Architecture Definition

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ARCHITECTURE behavior OF testbench IS

          COMPONENT ram

           Port ( address : in Integer range 0 to 15;

                  ce : in std_logic;

                  we : in std_logic;

                  oe : in std_logic;

                 data : inout std_logic_vector(7 downto 0));

          END COMPONENT;

signal address : Integer range 0 to 15;

signal ce : std_logic;

signal we : std_logic;

signal oe : std_logic;

signal data : std_logic_vector(7 downto 0);

BEGIN

          uut: ram PORT MAP(address => address,

                             ce => ce, oe => oe, we => we, data => data);

   testbench : PROCESS

   BEGIN

-- Set initial conditions

           wait for 0 ns;

           address <= 0; data <= "ZZZZZZZZ";

           ce <= '1'; we <= '1'; oe <= '1';

-- Write to memory address 0

           wait for 10 ns; data <= "01010101";

           wait for 10 ns; ce <= '0';

           wait for 10 ns; we <= '0';

           wait for 10 ns; ce <= '1'; we <= '1'; data <= "ZZZZZZZZ";

-- Write to memory address 1

          wait for 0 ns; address <= 1;

           wait for 10 ns; data <= "10101010";

           wait for 10 ns; ce <= '0';

           wait for 10 ns; we <= '0';

           wait for 10 ns; ce <= '1'; we <= '1'; data <= "ZZZZZZZZ";

-- Read from memory address 0

           wait for 0 ns; address <= 0;

           wait for 10 ns; ce <= '0';

           wait for 10 ns; oe <= '0';

           wait for 10 ns; ce <= '1'; oe <= '1';

-- Read from memory address 1

          wait for 0 ns; address <= 1;

           wait for 10 ns; ce <= '0';

           wait for 10 ns; oe <= '0';

           wait for 10 ns; ce <= '1'; oe <= '1';

          wait for 1 ms;

   END PROCESS;

END;

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-- End of File

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