*
Example HSPICE Input file to simulate a CMOS Weighted current DAC
**********************************************************************
*
Set Temperature and HSPICE Options
**********************************************************************
.TEMP
25
.OPTIONS
POST
**********************************************************************
*
Probe transistor drain currents
**********************************************************************
.PROBE
I(M1)
.PROBE
I(M2)
.PROBE
I(M3)
.PROBE
I(M4)
.PROBE
I(M5)
.PROBE
I(M6)
.PROBE
I(M7)
.PROBE
I(M8)
**********************************************************************
*
Set current and voltage reference sources
**********************************************************************
Iref
Vdd Gate
10uA
Vref
REF 0 2.5V
Vdd
Vdd 0 5V
**********************************************************************
*
Set digital input voltages (0V/+5V) in binary count
*
from 000 to 111 (+ inverters for complement signal)
**********************************************************************
Vd0
in0 0 PWL(0us,0V 1us,0V 1.01us,5V 2us,5V 2.01us,0V 3us,0V 3.01us,5V
+
4us,5V 4.01us,0V 5us,0V 5.01us,5V 6us,5V 6.01us,0V
+
7us,0V 7.01us,5V)
Minv0n
in0n in0
0 0
MODN W=1.0um
L=0.6um
Minv0p
in0n in0
Vdd Vdd
MODP W=2.5um
L=0.6um
Vd1
in1 0 PWL(0us,0V 2us,0V 2.01us,5V 4us,5V 4.01us,0V 6us,0V
6.01us,5V)
Minv1n
in1n in1
0 0
MODN W=1.0um
L=0.6um
Minv1p
in1n in1
Vdd Vdd
MODP W=2.5um
L=0.6um
Vd2
in2 0 PWL(0us,0V 4us,0V
4.01us,5V)
Minv2n
in2n in2
0 0
MODN W=1.0um
L=0.6um
Minv2p
in2n in2
Vdd Vdd
MODP W=2.5um
L=0.6um
**********************************************************************
*
Unit sized transistors (each transistor to carry 10uA)
**********************************************************************
M1
Gate Gate
0 0
MODN W=12.5um
L=10um
M2
D0 Gate
0 0
MODN W=12.5um
L=10um
M3
D1 Gate
0 0
MODN W=12.5um
L=10um
M4
D1 Gate
0 0 MODN W=12.5um
L=10um
M5
D2 Gate
0 0
MODN W=12.5um
L=10um
M6
D2 Gate
0 0
MODN W=12.5um
L=10um
M7
D2 Gate
0 0
MODN W=12.5um
L=10um
M8
D2 Gate
0 0
MODN W=12.5um
L=10um
**********************************************************************
*
Use CMOS transmission gates for switches
**********************************************************************
Msw0n1
NEG in0
D0 0
MODN W=2.5um
L=0.6um
Msw0p1
NEG in0n D0
Vdd MODP
W=7.5um L=0.6um
Msw0n2
POS in0n D0
0 MODN
W=2.5um L=0.6um
Msw0p2
POS in0
D0 Vdd
MODP W=7.5um
L=0.6um
Msw1n1
NEG in1
D1 0
MODN W=2.5um
L=0.6um
Msw1p1
NEG in1n D1
Vdd MODP
W=7.5um L=0.6um
Msw1n2
POS in1n D1
0 MODN
W=2.5um L=0.6um
Msw1p2
POS in1
D1 Vdd
MODP W=7.5um
L=0.6um
Msw2n1
NEG in2
D2 0
MODN W=2.5um
L=0.6um
Msw2p1
NEG in2n D2
Vdd MODP
W=7.5um L=0.6um
Msw2n2
POS in2n D2
0 MODN
W=2.5um L=0.6um
Msw2p2
POS in2
D2 Vdd
MODP W=7.5um
L=0.6um
**********************************************************************
*
OP-AMP Model and Resistors
**********************************************************************
E1
OUT 0 POS NEG
MAX=+5V MIN=0V
1e+5
R1
OUT NEG
20k
R2
REF POS
20k
**********************************************************************
*
Set transistor models
**********************************************************************
.model
MODN nMOS (LEVEL=1 VTO = 0.7 KP=25e-6
LAMBDA = 0)
.model
MODP pMOS (LEVEL=1 VTO = -0.7 KP=10e-6 LAMBDA = 0)
**********************************************************************
*
Run transient analysis
**********************************************************************
.Tran
0.1uS 8uS
**********************************************************************
*
End Simulation file
**********************************************************************
.END
**********************************************************************