--/////////////////////////////////////////

 -- Entity/Architecture description of an

 -- Inverter logic gate

 --/////////////////////////////////////////

 -- Input:-  A

 -- Output:- B

 --/////////////////////////////////////////

  -----------------------------------

  -- Entity Definition

  -----------------------------------

  ENTITY inverter_model IS

     PORT ( A     :      IN       STD_LOGIC;

            B    :      OUT       STD_LOGIC);

  end ENTITY inverter_model;

  -----------------------------------

  -- Architecture Definition

  -----------------------------------

  ARCHITECTURE simple OF inverter_model IS

  BEGIN

      B <= not (A);

  END ARCHITECTURE simple;