Integrated Circuit Test Engineering

Modern Techniques

CPLD Configuration

Introduction

The CPLD used in the design is the Lattice Semiconductor MACH4A5-64/32 CPLD. The configuration JEDEC file is located in the cpld directory as a  file named:

 fig_3_26.jed

This implements a UART transmitter and receiver, along with the circuit design for figure 3.26 in the main text. This JEDEC file is to be downloaded into the CPLD.

The top level schematic is provided as a PDF file.

The circuit under test schematic is provided as a PDF file.

The design is a mixture of VHDL code and schematics.