Integrated Circuit Test Engineering

Modern Techniques

Hardware Experimentation PCB Example

Introduction

An example of a possible implementation of the CPLD hardware experimentation is shown below. Here, a Lattice Semiconductor Inc. Mach 4A5-64/32 CPLD is utilised and is mounted on a Eurocard size PCB. This is a 2-sided PCB and connections on/off of the board are provided through two headers.

The image (JPG file) of the board can be viewed separately.

The RS-232 connector to/from the PC is sited to the left and the +5V power supply connector to the top. In this implementation, +5V digital logic only is supported.

The programming cable (Lattice Semiconductor Inc. cable) connector is sited to the left between the RS-232 and power supply connectors. Care will need to be taken to ensure that this connected correctly.

The basic equipment required can be shown separately.

The laboratory items are:

• Tester PCB (bottom right).

• RS-232 cable (top right).

• +5 volt (1 amp) power supply (top centre).

• Lattice Semiconductor programming cable and interface (top left). This unit can be purchased directly from Lattice Semiconductor.

With this board arrangement, the CPLD is driven by a 10 MHz crystal oscillator IC. A "Master Reset" switch is provided on the board to initialise the CPLD. The UART (transmitter and receiver) actions are performed within the CPLD itself, removing the need for an external UART (this also allows for a maximum number of pins to act as tester digital I/O through the header connectors located below (in the photograph) the CPLD. The CPLD is programmed from the PC via the Lattice Semiconductor interface unit and the PC parallel port.