# vsim "+altera" -L C:/altera/15.1lite/modelsim_ase/altera/verilog/cyclonev -L C:/altera/15.1lite/modelsim_ase/altera/verilog/altera -L C:/altera/15.1lite/modelsim_ase/altera/verilog/cyclonev -L C:/altera/15.1lite/modelsim_ase/altera/verilog/cyclonev_hssi -L C:/altera/15.1lite/modelsim_ase/altera/verilog/cyclonev_pcie_hip -L C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_mf -L C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim -l msim_transcript -gui work.fp_sqrt64 
# Start time: 13:38:57 on Jun 10,2019
# Loading work.fp_sqrt64
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera.dffeas
# Loading sv_std.std
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim.generic_m10k
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim.altera_lnsim_functions
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim.common_28nm_ram_block
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim.common_28nm_ram_register
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim.common_28nm_ram_pulse_generator
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera.PRIM_GDFF_LOW
# ** Warning: Design size of 18964 statements exceeds ModelSim Altera Starter recommended capacity.
# Expect performance to be adversely affected.
# hexadecimal
# 0 ps
# 493500 ps
dir *.v
#  Volume in drive E has no label.
#  Volume Serial Number is 9880-E3AF
# 
#  Directory of E:\DE1_SoC\DE1_SoC_CustomIPv
# 
# 06/08/2019  05:44 AM           124,128 fsqrt64.v
# 06/08/2019  05:44 AM               100 fsqrt64_inst.v
# 06/08/2019  05:44 AM             3,138 fsqrt64_bb.v
# 06/10/2019  01:40 PM             4,128 fp_sqrt64.v
# 06/10/2019  08:01 AM             1,703 DE1_SoC_CustomIPv.v
#                5 File(s)        133,197 bytes
#                0 Dir(s)  47,031,189,504 bytes free
vlog fp_sqrt64.v
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 13:41:01 on Jun 10,2019
# vlog -reportprogress 300 fp_sqrt64.v 
# -- Compiling module fp_sqrt64
# 
# Top level modules:
# 	fp_sqrt64
# End time: 13:41:04 on Jun 10,2019, Elapsed time: 0:00:03
# Errors: 0, Warnings: 0
do fp_sqrt64_vo.do
# fp_sqrt64
# ** Timing Simulation
# ** Warning: (vlib-34) Library already exists at "work".
# 
# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 13:56:40 on Jun 10,2019
# vlog -reportprogress 300 -work work fp_sqrt64.vo 
# -- Compiling module fp_sqrt64
# 
# Top level modules:
# 	fp_sqrt64
# End time: 13:56:50 on Jun 10,2019, Elapsed time: 0:00:10
# Errors: 0, Warnings: 0
# vsim "+altera" -L C:/altera/15.1lite/modelsim_ase/altera/verilog/cyclonev -L C:/altera/15.1lite/modelsim_ase/altera/verilog/altera -L C:/altera/15.1lite/modelsim_ase/altera/verilog/cyclonev -L C:/altera/15.1lite/modelsim_ase/altera/verilog/cyclonev_hssi -L C:/altera/15.1lite/modelsim_ase/altera/verilog/cyclonev_pcie_hip -L C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_mf -L C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim -l msim_transcript -gui work.fp_sqrt64 
# Start time: 13:56:51 on Jun 10,2019
# Loading work.fp_sqrt64
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera.dffeas
# Loading sv_std.std
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim.generic_m10k
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim.altera_lnsim_functions
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim.common_28nm_ram_block
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim.common_28nm_ram_register
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera_lnsim.common_28nm_ram_pulse_generator
# Loading C:/altera/15.1lite/modelsim_ase/altera/verilog/altera.PRIM_GDFF_LOW
# ** Warning: Design size of 18980 statements exceeds ModelSim Altera Starter recommended capacity.
# Expect performance to be adversely affected.
# hexadecimal
# 0 ps
# 493500 ps
# End time: 13:57:21 on Jun 10,2019, Elapsed time: 0:00:30
# Errors: 0, Warnings: 1
