Pseudorandom binary source
Model Name | PRBS(SHIFT_REGISTER)
Symbol |
Generics |
Name | Type | Default | Unit | Min | Max | Description
POLYGRAD | INTEGER | 2 | - | >1 | <35 | order of generator polynomial
SEED | BIT_VECTOR | "01" | - |  | <length(POLYGRAD) | initial bit vector of fsr
BIT_TIME | TIME | 1us | s | >0 |  | time duration of binary values
BIT_DEL | TIME | 0us | s | >=0 |  | initial time delay
Ports |
Interface | Name | Type/Nature | Mode | Description
signal | BIT_OUT | BIT | out | binary output
Description | This model describes a pseudorandom generator built up as a shift register with feedback. The register length can be choosen between 2 and 34. A generator polynomial is implemented which produces a sequence of maximum length.
Dependencies |
Logical Library | Design Unit/Design Entity
-- | Source:
Source | See source code