Sample and Hold Block
Model Name | SAMPLE_AND_HOLD(IDEAL)
Symbol |
Generics |
Name | Type | Default | Unit | Min | Description
TSAMPLE | REAL | 1.0E-3 | s | >0.0 | sampling time
DELAY | REAL | 0.0 | s | 0.0 | delay
Ports |
Interface | Name | Type/Nature | Description
terminal | INP | ELECTRICAL | controlling terminal
terminal | OUTP | ELECTRICAL | output terminal
Description | The input voltage is sampled after time DELAY. The model realizes a zero order sample and hold.
Dependencies |
Logical Library | Design Unit/Design Entity
IEEE_proposed | ELECTRICAL_SYSTEMS
Source | See source code
Example | See test-bench