Test-bench for A-to-D Converter
Model Name | BENCH(BENCH_A2D)
Description | A 1 kHz sinusoidal voltage is converted. Signal S_OUT_IDEAL is equal '1' for voltages greater than 0.0 and '0' for voltages less than 0.0. Signal S_OUT_EXTENDED is set to '1' when the voltage crosses 0.25. It is set to '0' when the voltage is less than -0.25. Simulation should run until 3 ms.
Dependencies |
Logical Library | Design Unit/Design Entity
IEEE_proposed | ELECTRICAL_SYSTEMS
IEEE | STD_LOGIC_1164
WORK | A2D(IDEAL)
WORK | A2D(EXTENDED)
Source | See source code
Results | See results