<?xml version="1.0" encoding="ISO-8859-1"?>
<?xml-stylesheet href="/usr/local/vamdoc-1.0.2-kluwer/config/model.xsl" type="text/xsl"?>
<!DOCTYPE model SYSTEM "/usr/local/vamdoc-1.0.2-kluwer/config/model.dtd"><model>
  <symbol>../symbol/a2d.png</symbol>
  <comments>
    <title>Analog-to-digital converter</title>
    <model_name>A2D(BHV_RF)</model_name>
    <library>N/A</library>
    <structure>N/A</structure>
    <description>This model describes an analog to digital converter. The conversion<br></br>is done by successive approximation in a digital process at every<br></br>rising clock edge.<br></br></description>
    <link_source><A HREF="../src/a2d.vhd">See source code</A></link_source>
    <dependency>
      <library>IEEE_proposed</library>
      <design_unit>ELECTRICAL_SYSTEMS</design_unit>
    </dependency>
    <dependency>
      <library>IEEE</library>
      <design_unit>MATH_REAL</design_unit>
    </dependency>
  </comments>
  <interface>
    <parameter>
      <name>PMAX_DBM</name>
      <type>REAL</type>
      <default>-100.0</default>
      <unit>dBm</unit>
      <comment> maximum power amplitude </comment>
    </parameter>
    <parameter>
      <name>RIN</name>
      <type>REAL</type>
      <default>50.0</default>
      <unit>Ohm</unit>
      <min> &gt;0.0</min>
      <comment> input resistance </comment>
    </parameter>
    <port>
      <port_id>terminal</port_id>
      <name>A</name>
      <port_type>ELECTRICAL</port_type>
      <comment> analog input</comment>
    </port>
    <port>
      <port_id>terminal</port_id>
      <name>GND</name>
      <port_type>ELECTRICAL</port_type>
      <comment> analog ground</comment>
    </port>
    <port>
      <port_id>signal</port_id>
      <name>D</name>
      <port_type>BIT_VECTOR</port_type>
      <mode>out</mode>
      <comment> digital output</comment>
    </port>
    <port>
      <port_id>signal</port_id>
      <name>CLK</name>
      <port_type>BIT</port_type>
      <mode>in</mode>
      <comment> clock input</comment>
    </port>
  </interface>
</model>
