<?xml version="1.0" encoding="ISO-8859-1"?>
<?xml-stylesheet href="/usr/local/vamdoc-1.0.2-kluwer/config/model.xsl" type="text/xsl"?>
<!DOCTYPE model SYSTEM "/usr/local/vamdoc-1.0.2-kluwer/config/model.dtd"><model>
  <symbol>../symbol/bench.png</symbol>
  <comments>
    <title>Analog PLL</title>
    <model_name>BENCH(PLL)</model_name>
    <library>N/A</library>
    <structure>N/A</structure>
    <description>The test-bench describes an analog PLL. The voltage at node N_IN<br></br>is frequency modulated by the first VCO (UUT2). The frequency modulated<br></br>voltage is available at node FM. This voltage is demodulated by the<br></br>PLL that consists of the phasedetector (UUT3), an analog filter (UUT4)<br></br>and the second VCO (UUT5). The demodulated voltage is available<br></br>at node OUT_PLL. The simulation should run until 200 us. <br></br></description>
    <link_source><A HREF="../src/bench.vhd">See source code</A></link_source>
    <dependency>
      <library>IEEE_proposed</library>
      <design_unit>ELECTRICAL_SYSTEMS</design_unit>
    </dependency>
    <dependency>
      <library>IEEE</library>
      <design_unit>MATH_REAL</design_unit>
    </dependency>
    <dependency>
      <library>WORK</library>
      <design_unit>VPWL(SPICE)</design_unit>
    </dependency>
    <dependency>
      <library>WORK</library>
      <design_unit>VCO(BASIC)</design_unit>
    </dependency>
    <dependency>
      <library>WORK</library>
      <design_unit>PD(BASIC)</design_unit>
    </dependency>
    <dependency>
      <library>WORK</library>
      <design_unit>FILTER(TP)</design_unit>
    </dependency>
  </comments>
  <interface>
  </interface>
</model>
