A-to-D Converter  
Model Name   A2D(IDEAL)
A2D(EXTENDED)
 
Symbol   No Symbol  
Generics  
Name   Type   Default   Unit   Min   Description  
LEVEL   REAL   2.5   V     threshold level  
HYST   REAL   0.0   V   >= 0.0   hysteresis  
 
Ports  
Interface   Name   Type/Nature   Default   Mode   Description  
terminal   INP   ELECTRICAL       controlling terminal  
signal   S_OUT   STD_LOGIC   '0'   out   output signal  
 
Description   The output signal is '1' if the input voltage is above LEVEL.
Otherwise it is '0'.
The architecture EXTENDED includes a hysteresis HYST.
Thus, changes to '1' occur at LEVEL+HYST/2. Changes to '0'
occur at LEVEL-HYST/2.

 
Dependencies  
Logical Library   Design Unit/Design Entity  
IEEE_proposed   ELECTRICAL_SYSTEMS  
IEEE   STD_LOGIC_1164  
 
Source   See source code  
Example   See test-bench