Test-bench for Delay Block
Model Name
BENCH(BENCH_DELAY)
Description
The sinusoidal voltage at node N_IN is delayed by 250 us.
The simulation should run until 2 ms.
Dependencies
Logical Library
Design Unit/Design Entity
IEEE_proposed
ELECTRICAL_SYSTEMS
WORK
DELAY_BLOCK(IDEAL)
Source
See source code
Results
See results