Analog PLL  
Model Name   BENCH(PLL)  
Description   The test-bench describes an analog PLL. The voltage at node N_IN
is frequency modulated by the first VCO (UUT2). The frequency modulated
voltage is available at node FM. This voltage is demodulated by the
PLL that consists of the phasedetector (UUT3), an analog filter (UUT4)
and the second VCO (UUT5). The demodulated voltage is available
at node OUT_PLL. The simulation should run until 200 us.
 
Dependencies  
Logical Library   Design Unit/Design Entity  
IEEE_proposed   ELECTRICAL_SYSTEMS  
IEEE   MATH_REAL  
WORK   VPWL(SPICE)  
WORK   VCO(BASIC)  
WORK   PD(BASIC)  
WORK   FILTER(TP)  
 
Source   See source code  
Results   See results