A-Law Companding
Model Name | COMPRESS(V1)
Symbol |
Generics |
Name | Type | Default | Unit | Min | Max | Description
K | POSITIVE | 1 |  | 1 | 6 | index for A array
VMAX | REAL | 1.0 | V | >0.0 |  | maximum voltage
Ports |
Interface | Name | Type/Nature | Description
terminal | INP | ELECTRICAL | controlling terminal
terminal | OUTP | ELECTRICAL | output terminal
Description | The model describes the A-law companding scheme that is used for signal compression. The input voltage must be between -VMAX and VMAX.
Dependencies |
Logical Library | Design Unit/Design Entity
IEEE_proposed | ELECTRICAL_SYSTEMS
IEEE | MATH_REAL
Source | See source code
Example | See test-bench