Delay Block
Model Name | DELAY_BLOCK(IDEAL)
Symbol |
Generics |
Name | Type | Default | Unit | Min | Description
T_DELAY | REAL |  | s | 0.0 | delay time
Ports |
Interface | Name | Type/Nature | Description
terminal | INP | ELECTRICAL | controlling terminal
terminal | OUTP | ELECTRICAL | output terminal
Description | The input voltage is delayed by time T_DELAY. The model realizes a voltage-controlled voltage source.
Dependencies |
Logical Library | Design Unit/Design Entity
IEEE_proposed | ELECTRICAL_SYSTEMS
Source | See source code
Example | See test-bench