Phase-locked loop
Model Name | PLL(LINEAR)
Symbol |
Generics |
Name | Type | Default | Unit | Description
VCO_TONE_DBM | REAL | -30.0 |  |
VCO_FREQ_0 | REAL | 1.0E06 |  |
VCO_K_FREQ | REAL | 1.0E09 |  |
MIX_GAIN_DB | REAL | 0.0 |  |
MIX_IIP3 | REAL | -10.0 |  |
LPF_GAIN_DB | REAL | 0.0 |  |
LPF_3DBFREQ | REAL | 1.0E5 |  |
LPF_GRADE | INTEGER | 1 |  |
Ports |
Interface | Name | Type/Nature | Description
terminal | P_REFCLK | ELECTRICAL |
terminal | P_OUT | ELECTRICAL |
terminal | P_OUTCLK | ELECTRICAL |
terminal | P_VDD | ELECTRICAL |
terminal | P_GND | ELECTRICAL |
Description | This model describes a linear analog Phase-locked loop. It consists of a multiplying mixer, an oscillator and a lowpass filter. The characteristics of the blocks can be parameterized.
References | Best, R.: Phase-locked loops: design, simulation, and applications. 5th edition, McGraw-Hill, 2003
Dependencies |
Logical Library | Design Unit/Design Entity
IEEE_proposed | ELECTRICAL_SYSTEMS
IEEE | MATH_REAL
WORK | VCO(ANALOG)
WORK | MIXER(RF)
WORK | LOWPASS(BHV_RF)
Source | See source code
Example | See test-bench