DIVIDER entity Declaration  
Model Name   DIVIDER  
Symbol   No Symbol  
Generics  
Name   Type   Default   Unit   Description  
N   POSITIVE       output pulse after N input pulses  
 
Ports  
Interface   Name   Type/Nature   Mode   Description  
signal   INP   BIT   IN   input  
signal   OUTP   BIT   out   output  
 
Description   The entity DIVIDER is declared. The architecture is described
in the file divider_simple.vhd. The entity is a primary design
unit. It has to be analyzed prior to the analysis of the
architecture.

 
Source   See source code  
Example   See test-bench