Simple Digital Divider
Model Name	BENCH(BENCH_SIMPLE)
Description	The BIT-value signal CLK changes its value after 1 ms. This signal is divided by the model DIVIDER(SIMPLE) using N=5. In an intervall of 10 ms there occur 5 pulses of CLK and one pulse of the dividers output OUTP. The simulation should run until 50 ms.
Dependencies	Logical Library   Design Unit/Design Entity   WORK   DIVIDER(SIMPLE)
Source	See source code
Results	See results