EMC for ICs > Models for EMC Simulation |

# Package Models

The package model is a key point of the emission prediction. The IBIS standard (Input/output IC Buffer Specification) includes a set of recommendations for modeling the package. The usual approach, valid up to several hundred of MHz, consists in a simple R,L,C model as shown in the figure. The inductor accounts for the lead and bonding serial inductance, the capacitor for the lead-to-ground capacitance and the resistance for the serial resistance of the conductor.

## Input Buffer I/O specification (IBIS)

Here is an example of IBIS description file, for a quad flat pack packaging and a 16 bit buffer. We see a list of keywords, followed by the description of each pin of the IC, with some electrical parameters such as serial inductor L_pkg, serial resistor C_Pkg and lead-to-ground capacitor C_pkg.

## R, L, C estimation

In this table, we give an estimation of the inductor L_pkg and the capacitor C_pkg. Their value range from 1 to 15nH for the inductance and 0.2 to 10pF for the capacitance. Some package feature significant difference between the shortest and the longest leads. Some package (QFP for example) have quite homogenous lead length, resulting in regular R,L,C parasitic parameters.

| Dual in Line (DIL) | 64 pins | L=2-15nH | C=1-10pF
| Shrink dual in line (SDIL) | 64 pins | L=1-10nH | C=1-10pF
| Small Outline package (SOP) | 64 pins | L=1-7nH | C=1-7pF
| Quad Flat Pack (QFP) | 400 pins | L=3-7nH | C=2-5pF

L_pkg = 1nH/mm, C_pkg = 0.2pF/mm

Modern packages, such as ball grid array BG, µBGA and chip-scale packaging, have very small serial inductance in some leads, but very high serial inductance for other leads. As these packages are usually targeted for 300 to 1000 I/O integrated circuits, the management of such a big packaging is hardly done by hand. Tools are thus required to define the appropriate floor-planning of I/Os, supply, noisy signal and sensitive signals according to the package layout.

| Ball gate Array (BGA) | 800 pins | L=0.5-10nH | C=1-10pF
| Fine Pitch Ball gate Array (FBGA) | 1500 pins | L=0.5-10nH | C=1-20pF
| Mold Chip Scale package (MCSP) | 1500 pins | L=0.5-5nH | C=1-15pF

Ball Gate Array |  |

## I/V of active devices (MOS, diodes)

The ibis description not only includes the package model. It also includes an approximation of the I/O response in terms of current. The knowledge of the current switching capability of the I/O is mandatory for emission prediction at printed circuit board level. This is why an I/V curve (In red in the figure) is given for each type of output buffer in the IBIS file.

EMC for ICs > Models for EMC Simulation > Package Models |