EMC problems handled at the end of design cycle
Conventional IC design methodologies consider the evaluation of parasitic emission level and susceptibility once the integrated circuit has been fabricated. Such methods often require a redesign with the help of EMC experts, which has a very import impact on the overall cost and time to market.
EMC validated before fabrication
Including reduction techniques in the early design phases and simulating the parasitic emission before fabrication, as suggested by low emission design methodologies, requires efficient IC models and adequate tools.
Models related to EMC start to appear, as well as specific tools to handle the EMC behaviour of the IC.
EMC for integrated circuits requires a wide amount of knowledge:
- High freq measurement techniques
- High freq modeling
- 2D, 3D modelling of conductors and structures
- Integrated circuit design
- Integrated circuit floorplan
EMC is at the cross point of several domains of exertise. Improving the electromagnetic compatibility of systems at chip level is a challenging task, which can be achieved through expert team working.
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