Golden Rules for Low Emission

Rule 1: Reduce the serial inductance

We detail four rules to reduce parasitic emission. The first one consists in decreasing the serial inductance. Inductance is a major component that creates resonance, and resonance is the source of conducted and radiated emission. The inductance is an intrinsic component of each conductor. When the conductor is far from ground, the inductance is increased. A bonding wire has approximately a 1nH/mm inductance. A supply line within the chip has a 0.2nH/mm inductance.

Why: because inductance is a major source of resonance
Where is the inductance: in each conductor, worst is far from ground

Exercise 1: target 150mV noise

In order to decrease the noise to 50mV, how many supply wires should be used?

Exercise 2: On-chip 8 bit ADC

In order to keep the on-chip analog-to-digital converter fully operational, how many supply wires should be used?

Avoid power lines on long leads

Some modern packaging such as the ball grid array (BGA) have lead length that vary significantly. Some leads are very short (1-2mm), some others are very long (1 cm).

The picture shows the internal structure of a BGA with 84 pins. Some BGA have up to 1500 pins.

Exercise 3: Place VDD and VSS on this BGA 84 (Rule of thumb: 2 supply for 8 I/Os)

The idea is to place VDD and VSS supply in balls close from the die of the integrated circuit. How many supply pins should be used? A rule of thumb proposes 2 supply for 8 I/Os.

Gains up to 5dB have been achieved in conducted mode by a careful assignment of supply pins.

Rule 2: Place VDD and VSS supply as close as possible

The second important rule consists is placing VDD and VSS supply as close as possible from each others. This reduces the surface of the current loop which provokes immediate parasitic emission, in radiated mode.

Why:

to reduce current loops that provoke magnetic field
to increase decoupling capacitance that reduces fluctuations

A very bad pin assignment consists in one VDD supply on one side, one VSS supply on the other side. This lead to a maximum emitted parasitic energy.

Consequently, the current wires placed together almost cancel the magnetic field and significantly reduce the radiated signature of the IC. Gains higher than 20dB have been observed in TEM cell measurements.

The good solution consists in the placement of VDD/VSS pad pairs. VDD/VSS rails should also be routed as close as possible. This increases decoupling capacitance. Also, multiple pairs significantly reduce the internal loops.

The best solution is to use a grid of supply network, for both VDD and VSS. This technique is widely used for CMOS technologies starting 0.35&micrro;m, where 5 metal layers or more are available.

Supply grid starting 0.35µm
Reduction of parasitic emission

Simulation of current flow on a grid

The distribution of current is rarely homogenous in all locations of the internal grid. Some parts handle small current density while other parts suffer strong current flows.

Rule 3: Add decoupling capacitance

An on-chip capacitance between V_DD and V_SS acts as a current generator that supplies the chip and thus reduces the amount of current flowing through the leads.

Why:

to keep the current flow internal
to reduce the supply voltage swing

An efficient technique to implement on-chip capacitance consists in routing VDD and VSS power rails large, on the top of each other, with multiple junction capacitance whenever possible. The free area underneath the routing channel can be used to implement extra capacitance. The thin oxide gate capacitance may be used to generate high value capacitance (several nF), with yield limits when implementing very large gate areas.

There are poor and good decoupling capacitor designs.

If the capacitor is placed far for the power rails, the resulting model is a LC circuit that behaves as an inductance at very high frequency. Consequently, the decoupling capacitance should be placed as close as possible to the current flow.

Rule 4: Identify & isolate Noisy blocks

The 4th important rule consists in trying to identify the noisy blocks, and try our best to isolate them. In terms of EMC, we concentrate on fast signals which switch high power. We try to supply these circuits by separate supplies, and if possible, isolate substrate noise conduction by a bulk isolation, a feature available starting 0.18µm.

Why:

to reduce the injected noise

How:

by locating fast signals with strong currents
by separate voltage supply
by substrate isolation

Identifying noisy sources is not a very easy task, as we need to find blocks with fast switching, with strong currents. The worst circuits are fast I/Os, oscillators, core circuits and data bus. Slow I/Os also may produce noise. Analog supply lines are much less noisy that core supply lines. Control lines that rarely switch do not cause much emission. Reset or Interrupt input signals almost never swing.

SIGNAL	Noisy
Fast I/Os	****
Oscillators	***
Core supply	**
Data bus	**
Slow I/Os	**
Analog supply	**
Control	*
Reset, interrupt

Using low drive output pads rather than high drive pads limits the charge and discharge current to 4 mA. In that case, the spectrum reduction is around 15 dB near 400MHz. Using high drive buffers increases the maximum current to 8 mA, which turns to significantly increase the conducted spectrum.

Many designers still choose high drive buffers to ensure that the electronic system goes fast. Not always strong buffers are required.