Macro-model of an IC

The IC model includes the core and package model

The macro-model of an IC consists of two main parts: one related to the core of the integrated circuit, the other one related to the package. Concerning the core, the internal switching activity is the main concern. The supply network also needs a careful analysis, as well as the active inputs and outputs.

Modelize the core

the internal activity
the supply network
the I/O structure

Modelize the Package using R,L,C

Concerning the package, an R,L,C matrix representing the interconnect array is required.

Modelize the core

The modeling of the core can be performed at various levels. We illustrate here three approaches. The first one, acting at physical level, consists in the analog simulation of the core. This approach is limited to small blocks, typically 100 to 1000 transistors. The current consumed on the VDD and VSS supply lines are accurately predicted.

Physical Transistor level (Spice)	Interpolated Transistor level (Powermill)	Gate level Activity (Verilog)

Huge simulation Limited to analog blocks	Difficult adaptation to usual tools Limited to 1 M devices	Simple, not limited Fast & accurate

For large blocks, a working approach consists in the use of pseudo analog simulation, where the physical set of equations is replaced by an approximated tabulated array of data. This approach speeds up considerably the simulation, which remains at analog level, and gives the current flow on VDD and VSS almost as accurately as for the pure analog simulation. However, the supply voltages are considered perfect. For several millions of devices, the only remaining approach is based on the gate current approximation, using a statistical approach for elementary gate current. The total current is the sum of elementary currents, each one being characterized individually under typical loading and switching conditions.

Here is the basic structure of the EMC model, as described in the international standard á ICEM â, promoted by the French standardization group UTE. The die is modeled by a capacitor Cd (Decoupling VDD/Vss), a serial access resistor Rvdd, Rvss, a serial inductor Lvdd, Lvss, a block decoupling Cd and a current generator Ib.

ICEM model promoted by UTE (IEC 62014-3)
Available in IBIS website www.eia.org/IBIS

This simple structure is able to predict quite accurately the consequences of the current flow in terms of supply noise and emitted energy in a TEM cell chamber.