Origin of Parasitic Emission

Basic mechanism for core current: CMOS inverter example

One of the major source of perturbation is the current flowing inside each elementary gate of the integrated circuit. Let us consider the CMOS inverter, supplied by a high voltage VDD (2V in 0.18µm) and ground VSS (0V). When the input falls to 0 (i.e logic level "0"), a current (around 0.5mA) charges the capacitance through the pull up device.

When the input rises to 2V, that is a logic level "1", a similar current flows through the pull down device and discharges the capacitance.

Exercise: CMOS inverter current waveform

The current versus time may be drawn as a 0.5mA peak on ISS at a fall edge of the output (equivalent to a rise edge of the input), and approximately the same peak on IDD at a rise of the output (equivalent to a fall edge at the input). Remember that a chip may include 250 Millions on devices, corresponding to approximately 50 Millions of elementary gates.

Due to synchronous design techniques, thousands of gates may switch at the same time, leading to current of several amperes within the chip.

Coupling mechanism

Two main coupling mechanisms may be distinguished: the conducted mode and the radiated mode. In conducted mode, the the parasitic perturbations are propagated from the main sources to the victims by interconnects. The supply lines are the main contributors to such coupling, as they are shared by several integrated circuits. Conducted coupling is the most common problem.

In the case of radiated mode, the source is able to generate a strong radiated energy, that couple through the air to a victim integrated circuit. Several cases radiated coupling may be found in electronic systems with embedded radio-frequency sources (Mobile phones for example).

Conducted mode	Radiated mode

The VDD supply propagates parasits	The EM wave propagates through the air