// ===========================================================
// RiseFall:  Shows effect of rise-fall delay values.
//
// ------------------------------------------------------------
// 2009-10-05 jmw: 2.0 Completely rewritten to exercise many
//                 new cases.   Integrated TB initial block.
// 2005-04-19 jmw: 1.1 Added 1-bit outputs.
// 2005-02-03 jmw: 1.0 implemented.
// ============================================================
//
`timescale 1ns/10ps
//
module RiseFall #(parameter tR=4, tF=3, tZ=5)
      ( output[7:0] OutBusRF, OutBusRFZ
      , OutBusRF_ALLR, OutBusRF_RevZ, OutBusRFZ_ALLR, OutBusRFZ_RevZ
      , OutBusRFZ_ALLZ1, OutBusRFZ_ALLZ0
      , output OutBitRF, OutBitRFZ, OutBitRFZ1, OutBitRFZ0
      );
//
reg[7:0] BusRFr, BusRFZr
       , BusRF_ALLRr, BusRF_RevZr, BusRFZ_ALLRr, BusRFZ_RevZr
       , BusRFZ_ALLZ1r, BusRFZ_ALLZ0r;
reg      BitRFr, BitRFZr, BitRFZ1r, BitRFZ0r;
reg Clk;
//
assign #(tR, tF)     OutBitRF       = BitRFr;
assign #(tR, tF, tZ) OutBitRFZ      = BitRFZr;
assign #(tR, tF, tZ) OutBitRFZ1     = BitRFZ1r;
assign #(tR, tF, tZ) OutBitRFZ0     = BitRFZ0r;
assign #(tR, tF)     OutBusRF       = BusRFr;
assign #(tR, tF, tZ) OutBusRFZ      = BusRFZr;
assign #(tR, tF)     OutBusRF_RevZ  = BusRF_RevZr;
assign #(tR, tF, tZ) OutBusRFZ_RevZ = BusRFZ_RevZr;
assign #(tR, tF)     OutBusRF_ALLR  = BusRF_ALLRr;
assign #(tR, tF, tZ) OutBusRFZ_ALLR = BusRFZ_ALLRr;
assign #(tR, tF, tZ) OutBusRFZ_ALLZ1 = BusRFZ_ALLZ1r;
assign #(tR, tF, tZ) OutBusRFZ_ALLZ0 = BusRFZ_ALLZ0r;
//
always@(posedge Clk)
  begin
  BusRFr        <= 8'b11zz_11xx;
  BusRFZr       <= 8'b10zz_10xx;
  BusRF_ALLRr   <= 8'b1111_1111;
  BusRF_RevZr   <= 8'bzzzz_1111;
  BusRFZ_ALLRr  <= 8'b1111_1111;
  BusRFZ_RevZr  <= 8'bzzzz_1111;
  BusRFZ_ALLZ1r <= 8'b1111_1111;
  BusRFZ_ALLZ0r <= 8'bzzzz_zzzz;
  BitRFr        <= 1'b1;
  BitRFZr       <= 1'b1;
  BitRFZ1r      <= 1'b1;
  BitRFZ0r      <= 1'bz;
  end
always@(negedge Clk)
  begin
  BusRFr        <= 8'b0010_zz00;
  BusRFZr       <= 8'b0110_zz10;
  BusRF_ALLRr   <= 8'b0000_0000;
  BusRF_RevZr   <= 8'b0000_zzzz;
  BusRFZ_ALLRr  <= 8'b0000_0000;
  BusRFZ_RevZr  <= 8'b0000_zzzz;
  BusRFZ_ALLZ1r <= 8'bzzzz_zzzz;
  BusRFZ_ALLZ0r <= 8'b0000_0000;
  BitRFr        <= 1'b0;
  BitRFZr       <= 1'b0;
  BitRFZ1r      <= 1'bz;
  BitRFZ0r      <= 1'b0;
  end
//
reg Clk;
always@(Clk) #10 Clk <= ~Clk;
//
initial
  begin
      Clk = 1'b0;
  #40 $finish;
  end
endmodule //RiseFall.
