
module PLLTop ( ClockOut, ClockIn, Reset );
  input ClockIn, Reset;
  output ClockOut;

initial $sdf_annotate("PLLTopNetlist.sdf");

  wire   n5, SampleWire, CtrCarry, n2, n3, n4;
  wire   [1:0] AdjFreq;

  DEL005 SampleDelay1 ( .I(ClockIn), .Z(SampleWire) );
  ClockComparator Comp1 ( .AdjustFreq(AdjFreq), .ClockIn(ClockIn), 
        .CounterClock(CtrCarry), .Reset(Reset) );
  VFO VFO1 ( .ClockOut(n5), .AdjustFreq(AdjFreq), .Sample(SampleWire), .Reset(
        Reset) );
  MultiCounter MCntr1 ( .CarryOut(CtrCarry), .Clock(n4), .Reset(Reset) );
  CKND16 U1 ( .CLK(n2), .CN(n3) );
  CKND16 U2 ( .CLK(n2), .CN(ClockOut) );
  CKND0 U3 ( .CLK(n5), .CN(n2) );
  BUFFD0 U4 ( .I(n3), .Z(n4) );
endmodule


module MultiCounter ( CarryOut, Clock, Reset );
  input Clock, Reset;
  output CarryOut;
  wire   N1, N2, N3, N4, N5, \add_16/carry[4] , \add_16/carry[3] ,
         \add_16/carry[2] , n1;
  wire   [3:0] Ctr;

  DFCNQD1 \Ctr_reg[1]  ( .D(N2), .CP(Clock), .CDN(n1), .Q(Ctr[1]) );
  DFCNQD1 \Ctr_reg[2]  ( .D(N3), .CP(Clock), .CDN(n1), .Q(Ctr[2]) );
  DFCNQD1 \Ctr_reg[3]  ( .D(N4), .CP(Clock), .CDN(n1), .Q(Ctr[3]) );
  DFCNQD1 \Ctr_reg[0]  ( .D(N1), .CP(Clock), .CDN(n1), .Q(Ctr[0]) );
  DFCNQD1 \Ctr_reg[4]  ( .D(N5), .CP(Clock), .CDN(n1), .Q(CarryOut) );
  INVD1 U3 ( .I(Reset), .ZN(n1) );
  HA1D0 U4 ( .A(Ctr[2]), .B(\add_16/carry[2] ), .CO(\add_16/carry[3] ), .S(N3)
         );
  HA1D0 U5 ( .A(Ctr[1]), .B(Ctr[0]), .CO(\add_16/carry[2] ), .S(N2) );
  HA1D0 U6 ( .A(Ctr[3]), .B(\add_16/carry[3] ), .CO(\add_16/carry[4] ), .S(N4)
         );
  INVD1 U7 ( .I(Ctr[0]), .ZN(N1) );
  CKXOR2D0 U8 ( .A1(\add_16/carry[4] ), .A2(CarryOut), .Z(N5) );
endmodule


module VFO ( ClockOut, AdjustFreq, Sample, Reset );
  input [1:0] AdjustFreq;
  input Sample, Reset;
  output ClockOut;
  wire   FastClock, N9, N10, N11, N12, N13, N15, N16, N17, N18, N19, N27, N28,
         N29, N30, N31, N35, N36, N37, N38, n12, n14, n15, n16, n17, n18,
         \add_183/carry[4] , \add_183/carry[3] , \add_183/carry[2] ,
         \add_164/carry[4] , \add_164/carry[3] , \add_164/carry[2] , n1, n2,
         n3, n4, n5, n6, n7, n8, n9, n10, n11, n13, n19, n20, n21, n22, n23,
         n24, n25, n26, n27, n28, n29;
  wire   [5:0] WireD;
  wire   [4:0] FastDivvy;
  wire   [4:0] DivideFactor;

  DEL005 \DelayLine[0].Delay83ps  ( .I(WireD[0]), .Z(WireD[1]) );
  DEL005 \DelayLine[1].Delay83ps  ( .I(WireD[1]), .Z(WireD[2]) );
  DEL005 \DelayLine[2].Delay83ps  ( .I(WireD[2]), .Z(WireD[3]) );
  DEL005 \DelayLine[3].Delay83ps  ( .I(WireD[3]), .Z(WireD[4]) );
  DEL005 \DelayLine[4].Delay83ps  ( .I(WireD[4]), .Z(WireD[5]) );
  CKND2D2 U23 ( .A1(WireD[5]), .A2(n1), .ZN(WireD[0]) );
  DFCNQD1 ClockOutReg_reg ( .D(n12), .CP(FastClock), .CDN(n29), .Q(ClockOut)
         );
  DFCNQD1 \FastDivvy_reg[4]  ( .D(N19), .CP(FastClock), .CDN(n29), .Q(
        FastDivvy[4]) );
  DFCNQD1 \FastDivvy_reg[2]  ( .D(N17), .CP(FastClock), .CDN(n1), .Q(
        FastDivvy[2]) );
  DFCNQD1 \FastDivvy_reg[3]  ( .D(N18), .CP(FastClock), .CDN(n1), .Q(
        FastDivvy[3]) );
  DFCNQD1 \FastDivvy_reg[1]  ( .D(N16), .CP(FastClock), .CDN(n1), .Q(
        FastDivvy[1]) );
  DFCNQD1 \FastDivvy_reg[0]  ( .D(N15), .CP(FastClock), .CDN(n1), .Q(
        FastDivvy[0]) );
  DFSNQD1 \DivideFactor_reg[4]  ( .D(n17), .CP(Sample), .SDN(n1), .Q(
        DivideFactor[4]) );
  DFSNQD1 \DivideFactor_reg[0]  ( .D(n18), .CP(Sample), .SDN(n1), .Q(
        DivideFactor[0]) );
  DFCNQD1 \DivideFactor_reg[2]  ( .D(n15), .CP(Sample), .CDN(n1), .Q(
        DivideFactor[2]) );
  DFCNQD1 \DivideFactor_reg[3]  ( .D(n14), .CP(Sample), .CDN(n1), .Q(
        DivideFactor[3]) );
  DFSND1 \DivideFactor_reg[1]  ( .D(n16), .CP(Sample), .SDN(n29), .Q(
        DivideFactor[1]), .QN(n28) );
  BUFFD1 U3 ( .I(n29), .Z(n1) );
  INVD1 U4 ( .I(Reset), .ZN(n29) );
  INVD1 U5 ( .I(DivideFactor[0]), .ZN(N27) );
  HA1D0 U6 ( .A(DivideFactor[2]), .B(\add_183/carry[2] ), .CO(
        \add_183/carry[3] ), .S(N29) );
  HA1D0 U7 ( .A(DivideFactor[1]), .B(DivideFactor[0]), .CO(\add_183/carry[2] ), 
        .S(N28) );
  HA1D0 U8 ( .A(DivideFactor[3]), .B(\add_183/carry[3] ), .CO(
        \add_183/carry[4] ), .S(N30) );
  INVD1 U9 ( .I(DivideFactor[2]), .ZN(n5) );
  INVD1 U10 ( .I(FastDivvy[0]), .ZN(N9) );
  HA1D0 U11 ( .A(FastDivvy[1]), .B(FastDivvy[0]), .CO(\add_164/carry[2] ), .S(
        N10) );
  HA1D0 U12 ( .A(FastDivvy[2]), .B(\add_164/carry[2] ), .CO(\add_164/carry[3] ), .S(N11) );
  HA1D0 U13 ( .A(FastDivvy[3]), .B(\add_164/carry[3] ), .CO(\add_164/carry[4] ), .S(N12) );
  CKXOR2D0 U14 ( .A1(\add_164/carry[4] ), .A2(FastDivvy[4]), .Z(N13) );
  CKXOR2D0 U15 ( .A1(\add_183/carry[4] ), .A2(DivideFactor[4]), .Z(N31) );
  NR2D0 U16 ( .A1(DivideFactor[1]), .A2(DivideFactor[0]), .ZN(n2) );
  AO21D0 U17 ( .A1(DivideFactor[0]), .A2(DivideFactor[1]), .B(n2), .Z(N35) );
  CKND2D0 U18 ( .A1(n2), .A2(n5), .ZN(n3) );
  OAI21D0 U19 ( .A1(n2), .A2(n5), .B(n3), .ZN(N36) );
  XNR2D0 U20 ( .A1(n3), .A2(DivideFactor[3]), .ZN(N37) );
  NR2D0 U21 ( .A1(DivideFactor[3]), .A2(n3), .ZN(n4) );
  CKXOR2D0 U22 ( .A1(DivideFactor[4]), .A2(n4), .Z(N38) );
  AO222D0 U24 ( .A1(N27), .A2(n6), .B1(N27), .B2(n7), .C1(DivideFactor[0]), 
        .C2(n8), .Z(n18) );
  AO222D0 U25 ( .A1(N31), .A2(n6), .B1(N38), .B2(n7), .C1(DivideFactor[4]), 
        .C2(n8), .Z(n17) );
  AO222D0 U26 ( .A1(N28), .A2(n6), .B1(N35), .B2(n7), .C1(DivideFactor[1]), 
        .C2(n8), .Z(n16) );
  AO222D0 U27 ( .A1(N29), .A2(n6), .B1(N36), .B2(n7), .C1(DivideFactor[2]), 
        .C2(n8), .Z(n15) );
  AO222D0 U28 ( .A1(N30), .A2(n6), .B1(N37), .B2(n7), .C1(DivideFactor[3]), 
        .C2(n8), .Z(n14) );
  NR2D0 U29 ( .A1(n8), .A2(n9), .ZN(n7) );
  NR2D0 U30 ( .A1(n8), .A2(AdjustFreq[0]), .ZN(n6) );
  MUX2D0 U31 ( .I0(n10), .I1(n11), .S(AdjustFreq[1]), .Z(n8) );
  OAI21D0 U32 ( .A1(DivideFactor[4]), .A2(DivideFactor[3]), .B(AdjustFreq[0]), 
        .ZN(n11) );
  CKND2D0 U33 ( .A1(n9), .A2(n13), .ZN(n10) );
  ND4D0 U34 ( .A1(DivideFactor[4]), .A2(DivideFactor[3]), .A3(DivideFactor[2]), 
        .A4(DivideFactor[1]), .ZN(n13) );
  CKND0 U35 ( .CLK(AdjustFreq[0]), .CN(n9) );
  XNR2D0 U36 ( .A1(ClockOut), .A2(n19), .ZN(n12) );
  AN2D0 U37 ( .A1(N13), .A2(n19), .Z(N19) );
  AN2D0 U38 ( .A1(N12), .A2(n19), .Z(N18) );
  AN2D0 U39 ( .A1(N11), .A2(n19), .Z(N17) );
  AN2D0 U40 ( .A1(N10), .A2(n19), .Z(N16) );
  AN2D0 U41 ( .A1(N9), .A2(n19), .Z(N15) );
  IOA21D0 U42 ( .A1(n20), .A2(DivideFactor[4]), .B(n21), .ZN(n19) );
  OAI221D0 U43 ( .A1(DivideFactor[3]), .A2(n22), .B1(DivideFactor[4]), .B2(n20), .C(n23), .ZN(n21) );
  AO222D0 U44 ( .A1(n24), .A2(DivideFactor[2]), .B1(n25), .B2(n26), .C1(n22), 
        .C2(DivideFactor[3]), .Z(n23) );
  OR2D0 U45 ( .A1(DivideFactor[2]), .A2(n24), .Z(n26) );
  CKND0 U46 ( .CLK(FastDivvy[2]), .CN(n25) );
  OAI32D0 U47 ( .A1(N27), .A2(FastDivvy[0]), .A3(n27), .B1(FastDivvy[1]), .B2(
        n28), .ZN(n24) );
  INR2D0 U48 ( .A1(FastDivvy[1]), .B1(DivideFactor[1]), .ZN(n27) );
  CKND0 U49 ( .CLK(FastDivvy[3]), .CN(n22) );
  CKND0 U50 ( .CLK(FastDivvy[4]), .CN(n20) );
  CKND0 U51 ( .CLK(WireD[0]), .CN(FastClock) );
endmodule


module ClockComparator ( AdjustFreq, ClockIn, CounterClock, Reset );
  output [1:0] AdjustFreq;
  input ClockIn, CounterClock, Reset;
  wire   \ClockInN[0] , N6, \CounterClockN[1] , N8, N39, N40, n5, n8, n9, n10,
         n4, n6, n7, n11;

  IAO21D1 U7 ( .A1(n6), .A2(n9), .B(N40), .ZN(n10) );
  DFCND1 \CounterClockN_reg[0]  ( .D(n8), .CP(CounterClock), .CDN(n4), .QN(n8)
         );
  DFSNQD1 \AdjustFreqR_reg[0]  ( .D(n7), .CP(CounterClock), .SDN(n11), .Q(
        AdjustFreq[0]) );
  DFCNQD1 \AdjustFreqR_reg[1]  ( .D(N39), .CP(CounterClock), .CDN(n11), .Q(
        AdjustFreq[1]) );
  DFCNQD1 \CounterClockN_reg[1]  ( .D(N8), .CP(CounterClock), .CDN(n4), .Q(
        \CounterClockN[1] ) );
  DFCNQD1 \ClockInN_reg[0]  ( .D(n6), .CP(ClockIn), .CDN(n4), .Q(\ClockInN[0] ) );
  DFCND1 \ClockInN_reg[1]  ( .D(N6), .CP(ClockIn), .CDN(n4), .QN(n5) );
  DFSND1 ZeroCounters_reg ( .D(N40), .CP(ClockIn), .SDN(n11), .QN(n4) );
  INVD1 U3 ( .I(Reset), .ZN(n11) );
  INVD1 U4 ( .I(\ClockInN[0] ), .ZN(n6) );
  NR2D1 U5 ( .A1(n5), .A2(n6), .ZN(N40) );
  XNR2D1 U6 ( .A1(n5), .A2(\ClockInN[0] ), .ZN(N6) );
  OAI22D0 U8 ( .A1(n9), .A2(n5), .B1(N8), .B2(n10), .ZN(N39) );
  NR2D1 U9 ( .A1(n7), .A2(n8), .ZN(n9) );
  XNR2D1 U10 ( .A1(\CounterClockN[1] ), .A2(n8), .ZN(N8) );
  INVD1 U11 ( .I(\CounterClockN[1] ), .ZN(n7) );
endmodule

