
module Intro_Top ( X, Y, Z, ScanOut, A, B, C, D, ScanIn, ScanMode, ScanClk, 
        ScanRst );
  input A, B, C, D, ScanIn, ScanMode, ScanClk, ScanRst;
  output X, Y, Z, ScanOut;
  wire   qn, ab, bc, fromA, fromB, fromC, q, fromD, toX, toY, n1, n2, n3, n4,
         n5, n6, n7, n8, n9, Intro_Top_inv_in, Intro_Top_tdi, Intro_Top_tdo,
         Intro_Top_tdo_en, net419, Intro_Top_tms, Intro_Top_trst_n,
         \Intro_Top_instructions[0] , \Intro_Top_instructions[1] ,
         Intro_Top_bypass_sel, net498, net500, Intro_Top_INV_ABC_2,
         Intro_Top_data_in, Intro_Top_data_in_1, Intro_Top_data_in_2,
         Intro_Top_data_in_3, Intro_Top_data_out, Intro_Top_data_out_1,
         Intro_Top_data_out_2, Intro_Top_si_6, net519, net541, net542, net543,
         net544, net545, net546, net547, net548, net549, net550, net551,
         net552, net553, net554, net555, net556, net557, net558, net559,
         net560, net561, net562, net563, net564, net565, net566, net567,
         net568, net569, net570, net571, net572, net573, net574, net575,
         net576, net577, net578, net579, net580, net581, net582, net583,
         net584, net585, net586, net587, net588, net589, net590, net591,
         net592, net593, net594, net595, net596, net597, net598, net599,
         net600, net601, net602, net603, net604, net605, net606, net607,
         net608, net609, net610;
  tri   ScanOut;

  AndOr InputCombo01 ( .X(ab), .Y(bc), .A(n5), .B(n9), .C(n3) );
  SR SRLatch01 ( .Q(q), .Qn(qn), .S(bc), .R(n7) );
  XorNor OutputCombo01 ( .X(toX), .Y(toY), .A(ab), .B(q), .C(qn) );
  PDC0204CDG_18_Out Xpad1 ( .I(Intro_Top_data_out), .PAD(X) );
  PDC0204CDG_18_Out Ypad1 ( .I(Intro_Top_data_out_1), .PAD(Y) );
  PDC0204CDG_18_Out Zpad1 ( .I(Intro_Top_data_out_2), .PAD(Z) );
  PDC0204CDG_18_In padA1 ( .PAD(A), .C(Intro_Top_data_in) );
  PDC0204CDG_18_In padB1 ( .PAD(B), .C(Intro_Top_data_in_1) );
  PDC0204CDG_18_In padC1 ( .PAD(C), .C(Intro_Top_data_in_2) );
  PDC0204CDG_18_In padD1 ( .PAD(D), .C(Intro_Top_data_in_3) );
  PDC0204CDG_18_Tri TDOpad1 ( .I(Intro_Top_tdo), .OEN(Intro_Top_tdo_en), .PAD(
        ScanOut) );
  PDC0204CDG_18_In padTMS1 ( .PAD(ScanMode), .C(Intro_Top_tms) );
  PDC0204CDG_18_In padTDI1 ( .PAD(ScanIn), .C(Intro_Top_tdi) );
  PDC0204CDG_18_In padTCK1 ( .PAD(ScanClk), .C(Intro_Top_inv_in) );
  PDC0204CDG_18_In padTRST1 ( .PAD(ScanRst), .C(Intro_Top_trst_n) );
  INVD0 U2 ( .I(fromC), .ZN(n2) );
  INVD0 U3 ( .I(n2), .ZN(n3) );
  INVD0 U4 ( .I(fromA), .ZN(n4) );
  INVD0 U5 ( .I(n4), .ZN(n5) );
  INVD0 U6 ( .I(fromD), .ZN(n6) );
  INVD0 U7 ( .I(n6), .ZN(n7) );
  INVD0 U8 ( .I(fromB), .ZN(n8) );
  INVD0 U9 ( .I(n8), .ZN(n9) );
  CKND0 U10 ( .CLK(qn), .CN(n1) );
  Intro_Top_DW_tap_uc_width2_id0_idcode_opcode1_version0_part0_man_num0_sync_mode1 Intro_Top_DW_tap_inst ( 
        .tck(Intro_Top_inv_in), .trst_n(Intro_Top_trst_n), .tms(Intro_Top_tms), 
        .tdi(Intro_Top_tdi), .so(Intro_Top_si_6), .bypass_sel(
        Intro_Top_bypass_sel), .sentinel_val(net541), .device_id_sel(net542), 
        .user_code_sel(net543), .user_code_val({net544, net545, net546, net547, 
        net548, net549, net550, net551, net552, net553, net554, net555, net556, 
        net557, net558, net559, net560, net561, net562, net563, net564, net565, 
        net566, net567, net568, net569, net570, net571, net572, net573, net574, 
        net575}), .ver({net576, net577, net578, net579}), .ver_sel(net580), 
        .part_num({net581, net582, net583, net584, net585, net586, net587, 
        net588, net589, net590, net591, net592, net593, net594, net595, net596}), .part_num_sel(net597), .mnfr_id({net598, net599, net600, net601, net602, 
        net603, net604, net605, net606, net607, net608}), .mnfr_id_sel(net609), 
        .clock_dr(net519), .shift_dr(Intro_Top_INV_ABC_2), .tdo(Intro_Top_tdo), 
        .tdo_en(net419), .instructions({\Intro_Top_instructions[1] , 
        \Intro_Top_instructions[0] }), .sync_capture_en(net498), 
        .sync_update_dr(net500), .test(net610) );
  Intro_Top_BSR_top_inst_design Intro_Top_BSR_top_inst ( .toY(toY), .toX(toX), 
        .net519(net519), .net500(net500), .net498(net498), .net419(net419), 
        .n1(n1), .fromD(fromD), .fromC(fromC), .fromB(fromB), .fromA(fromA), 
        .Intro_Top_tdo_en(Intro_Top_tdo_en), .Intro_Top_tdi(Intro_Top_tdi), 
        .Intro_Top_si_6(Intro_Top_si_6), .Intro_Top_inv_in(Intro_Top_inv_in), 
        .\Intro_Top_instructions[1] (\Intro_Top_instructions[1] ), 
        .\Intro_Top_instructions[0] (\Intro_Top_instructions[0] ), 
        .Intro_Top_data_out_2(Intro_Top_data_out_2), .Intro_Top_data_out_1(
        Intro_Top_data_out_1), .Intro_Top_data_out(Intro_Top_data_out), 
        .Intro_Top_data_in_3(Intro_Top_data_in_3), .Intro_Top_data_in_2(
        Intro_Top_data_in_2), .Intro_Top_data_in_1(Intro_Top_data_in_1), 
        .Intro_Top_data_in(Intro_Top_data_in), .Intro_Top_bypass_sel(
        Intro_Top_bypass_sel), .Intro_Top_INV_ABC_2(Intro_Top_INV_ABC_2) );
endmodule


module Intro_Top_BSR_top_inst_design ( toY, toX, net519, net500, net498, 
        net419, n1, fromD, fromC, fromB, fromA, Intro_Top_tdo_en, 
        Intro_Top_tdi, Intro_Top_si_6, Intro_Top_inv_in, 
        \Intro_Top_instructions[1] , \Intro_Top_instructions[0] , 
        Intro_Top_data_out_2, Intro_Top_data_out_1, Intro_Top_data_out, 
        Intro_Top_data_in_3, Intro_Top_data_in_2, Intro_Top_data_in_1, 
        Intro_Top_data_in, Intro_Top_bypass_sel, Intro_Top_INV_ABC_2 );
  input toY, toX, net519, net500, net498, net419, n1, Intro_Top_tdi,
         Intro_Top_inv_in, \Intro_Top_instructions[1] ,
         \Intro_Top_instructions[0] , Intro_Top_data_in_3, Intro_Top_data_in_2,
         Intro_Top_data_in_1, Intro_Top_data_in, Intro_Top_INV_ABC_2;
  output fromD, fromC, fromB, fromA, Intro_Top_tdo_en, Intro_Top_si_6,
         Intro_Top_data_out_2, Intro_Top_data_out_1, Intro_Top_data_out,
         Intro_Top_bypass_sel;
  wire   EXTEST, Intro_Top_INV_ABC, Intro_Top_INV_ABC_1, Intro_Top_si,
         Intro_Top_si_1, Intro_Top_si_2, Intro_Top_si_3, Intro_Top_si_4,
         Intro_Top_si_5, tck;

  Intro_Top_DW_bc_2_test_0 Intro_Top_A_bsr1 ( .capture_clk(Intro_Top_inv_in), 
        .update_clk(tck), .capture_en(Intro_Top_INV_ABC), .update_en(
        Intro_Top_INV_ABC_1), .shift_dr(Intro_Top_INV_ABC_2), .mode(1'b0), 
        .si(Intro_Top_tdi), .data_in(Intro_Top_data_in), .data_out(fromA), 
        .so(Intro_Top_si) );
  Intro_Top_DW_bc_2_test_1 Intro_Top_B_bsr2 ( .capture_clk(Intro_Top_inv_in), 
        .update_clk(tck), .capture_en(Intro_Top_INV_ABC), .update_en(
        Intro_Top_INV_ABC_1), .shift_dr(Intro_Top_INV_ABC_2), .mode(1'b0), 
        .si(Intro_Top_si), .data_in(Intro_Top_data_in_1), .data_out(fromB), 
        .so(Intro_Top_si_1) );
  Intro_Top_DW_bc_2_test_2 Intro_Top_C_bsr3 ( .capture_clk(Intro_Top_inv_in), 
        .update_clk(tck), .capture_en(Intro_Top_INV_ABC), .update_en(
        Intro_Top_INV_ABC_1), .shift_dr(Intro_Top_INV_ABC_2), .mode(1'b0), 
        .si(Intro_Top_si_1), .data_in(Intro_Top_data_in_2), .data_out(fromC), 
        .so(Intro_Top_si_2) );
  Intro_Top_DW_bc_2 Intro_Top_D_bsr4 ( .capture_clk(Intro_Top_inv_in), 
        .update_clk(tck), .capture_en(Intro_Top_INV_ABC), .update_en(
        Intro_Top_INV_ABC_1), .shift_dr(Intro_Top_INV_ABC_2), .mode(1'b0), 
        .si(Intro_Top_si_2), .data_in(Intro_Top_data_in_3), .data_out(fromD), 
        .so(Intro_Top_si_3) );
  Intro_Top_DW_bc_1_test_0 Intro_Top_X_bsr5 ( .capture_clk(Intro_Top_inv_in), 
        .update_clk(tck), .capture_en(Intro_Top_INV_ABC), .update_en(
        Intro_Top_INV_ABC_1), .shift_dr(Intro_Top_INV_ABC_2), .mode(EXTEST), 
        .si(Intro_Top_si_3), .data_in(toX), .data_out(Intro_Top_data_out), 
        .so(Intro_Top_si_4) );
  Intro_Top_DW_bc_1_test_1 Intro_Top_Y_bsr6 ( .capture_clk(Intro_Top_inv_in), 
        .update_clk(tck), .capture_en(Intro_Top_INV_ABC), .update_en(
        Intro_Top_INV_ABC_1), .shift_dr(Intro_Top_INV_ABC_2), .mode(EXTEST), 
        .si(Intro_Top_si_4), .data_in(toY), .data_out(Intro_Top_data_out_1), 
        .so(Intro_Top_si_5) );
  Intro_Top_DW_bc_1 Intro_Top_Z_bsr7 ( .capture_clk(Intro_Top_inv_in), 
        .update_clk(tck), .capture_en(Intro_Top_INV_ABC), .update_en(
        Intro_Top_INV_ABC_1), .shift_dr(Intro_Top_INV_ABC_2), .mode(EXTEST), 
        .si(Intro_Top_si_5), .data_in(n1), .data_out(Intro_Top_data_out_2), 
        .so(Intro_Top_si_6) );
  Intro_Top_BSR_mode_inst_design Intro_Top_BSR_mode_inst ( .tck(tck), .net519(
        net519), .net500(net500), .net498(net498), .net419(net419), 
        .Intro_Top_tdo_en(Intro_Top_tdo_en), .Intro_Top_inv_in(
        Intro_Top_inv_in), .\Intro_Top_instructions[1] (
        \Intro_Top_instructions[1] ), .\Intro_Top_instructions[0] (
        \Intro_Top_instructions[0] ), .Intro_Top_bypass_sel(
        Intro_Top_bypass_sel), .Intro_Top_INV_ABC_2(Intro_Top_INV_ABC_2), 
        .Intro_Top_INV_ABC_1(Intro_Top_INV_ABC_1), .Intro_Top_INV_ABC(
        Intro_Top_INV_ABC), .EXTEST(EXTEST) );
endmodule


module Intro_Top_BSR_mode_inst_design ( tck, net519, net500, net498, net419, 
        Intro_Top_tdo_en, Intro_Top_inv_in, \Intro_Top_instructions[1] , 
        \Intro_Top_instructions[0] , Intro_Top_bypass_sel, Intro_Top_INV_ABC_2, 
        Intro_Top_INV_ABC_1, Intro_Top_INV_ABC, EXTEST );
  input net519, net500, net498, net419, Intro_Top_inv_in,
         \Intro_Top_instructions[1] , \Intro_Top_instructions[0] ,
         Intro_Top_INV_ABC_2;
  output tck, Intro_Top_tdo_en, Intro_Top_bypass_sel, Intro_Top_INV_ABC_1,
         Intro_Top_INV_ABC, EXTEST;
  wire   BYPASS, PRELOAD, SAMPLE, net702, net701, net700, net699, net698,
         net697, net696, net695;

  CKND0 \*cell*806  ( .CLK(net498), .CN(net699) );
  CKND0 \*cell*805  ( .CLK(EXTEST), .CN(net700) );
  CKND0 \*cell*804  ( .CLK(SAMPLE), .CN(net701) );
  CKND0 \*cell*803  ( .CLK(PRELOAD), .CN(net702) );
  ND3D1 \*cell*802  ( .A1(net700), .A2(net701), .A3(net702), .ZN(net696) );
  CKND2D0 \*cell*801  ( .A1(net699), .A2(net696), .ZN(Intro_Top_INV_ABC) );
  CKND0 \*cell*800  ( .CLK(net696), .CN(net697) );
  CKND0 \*cell*799  ( .CLK(net500), .CN(net698) );
  NR2XD0 \*cell*798  ( .A1(net697), .A2(net698), .ZN(Intro_Top_INV_ABC_1) );
  CKND0 \*cell*797  ( .CLK(BYPASS), .CN(net695) );
  CKND2D0 \*cell*796  ( .A1(net695), .A2(net696), .ZN(Intro_Top_bypass_sel) );
  CKND0 \*cell*795  ( .CLK(net419), .CN(Intro_Top_tdo_en) );
  CKND0 \*cell*794  ( .CLK(Intro_Top_inv_in), .CN(tck) );
  Intro_Top_Decoder_inst_design Intro_Top_Decoder_inst ( .SAMPLE(SAMPLE), 
        .PRELOAD(PRELOAD), .\Intro_Top_instructions[1] (
        \Intro_Top_instructions[1] ), .\Intro_Top_instructions[0] (
        \Intro_Top_instructions[0] ), .EXTEST(EXTEST), .BYPASS(BYPASS) );
endmodule


module Intro_Top_Decoder_inst_design ( SAMPLE, PRELOAD, 
        \Intro_Top_instructions[1] , \Intro_Top_instructions[0] , EXTEST, 
        BYPASS );
  input \Intro_Top_instructions[1] , \Intro_Top_instructions[0] ;
  output SAMPLE, PRELOAD, EXTEST, BYPASS;
  wire   net671, net676;
  assign PRELOAD = net676;

  AN2XD1 \*cell*788  ( .A1(\Intro_Top_instructions[1] ), .A2(
        \Intro_Top_instructions[0] ), .Z(BYPASS) );
  NR2XD0 \*cell*787  ( .A1(\Intro_Top_instructions[1] ), .A2(
        \Intro_Top_instructions[0] ), .ZN(EXTEST) );
  IND2D0 \*cell*786  ( .A1(\Intro_Top_instructions[1] ), .B1(
        \Intro_Top_instructions[0] ), .ZN(net671) );
  CKND0 \*cell*785  ( .CLK(net671), .CN(SAMPLE) );
  BUFFD16 \*cell*792  ( .I(SAMPLE), .Z(net676) );
endmodule


module Intro_Top_DW_bc_1 ( capture_clk, update_clk, capture_en, update_en, 
        shift_dr, mode, si, data_in, data_out, so );
  input capture_clk, update_clk, capture_en, update_en, shift_dr, mode, si,
         data_in;
  output data_out, so;
  wire   temp_out, \U1/U1/ffin , \U1/ffin ;

  MUX3D1 \*cell*623  ( .I0(data_in), .I1(si), .I2(so), .S0(shift_dr), .S1(
        capture_en), .Z(\U1/U1/ffin ) );
  CKMUX2D0 \*cell*622  ( .I0(temp_out), .I1(so), .S(update_en), .Z(\U1/ffin )
         );
  CKMUX2D0 \*cell*621  ( .I0(data_in), .I1(temp_out), .S(mode), .Z(data_out)
         );
  DFD2 \U1/U1/U3  ( .D(\U1/U1/ffin ), .CP(capture_clk), .Q(so) );
  DFD2 \U1/U3  ( .D(\U1/ffin ), .CP(update_clk), .Q(temp_out) );
endmodule


module Intro_Top_DW_bc_1_test_1 ( capture_clk, update_clk, capture_en, 
        update_en, shift_dr, mode, si, data_in, data_out, so );
  input capture_clk, update_clk, capture_en, update_en, shift_dr, mode, si,
         data_in;
  output data_out, so;
  wire   temp_out, \U1/U1/ffin , \U1/ffin ;

  MUX3D1 \*cell*623  ( .I0(data_in), .I1(si), .I2(so), .S0(shift_dr), .S1(
        capture_en), .Z(\U1/U1/ffin ) );
  CKMUX2D0 \*cell*622  ( .I0(temp_out), .I1(so), .S(update_en), .Z(\U1/ffin )
         );
  CKMUX2D0 \*cell*621  ( .I0(data_in), .I1(temp_out), .S(mode), .Z(data_out)
         );
  DFD2 \U1/U1/U3  ( .D(\U1/U1/ffin ), .CP(capture_clk), .Q(so) );
  DFD2 \U1/U3  ( .D(\U1/ffin ), .CP(update_clk), .Q(temp_out) );
endmodule


module Intro_Top_DW_bc_1_test_0 ( capture_clk, update_clk, capture_en, 
        update_en, shift_dr, mode, si, data_in, data_out, so );
  input capture_clk, update_clk, capture_en, update_en, shift_dr, mode, si,
         data_in;
  output data_out, so;
  wire   temp_out, \U1/U1/ffin , \U1/ffin ;

  MUX3D1 \*cell*623  ( .I0(data_in), .I1(si), .I2(so), .S0(shift_dr), .S1(
        capture_en), .Z(\U1/U1/ffin ) );
  CKMUX2D0 \*cell*622  ( .I0(temp_out), .I1(so), .S(update_en), .Z(\U1/ffin )
         );
  CKMUX2D0 \*cell*621  ( .I0(data_in), .I1(temp_out), .S(mode), .Z(data_out)
         );
  DFD2 \U1/U1/U3  ( .D(\U1/U1/ffin ), .CP(capture_clk), .Q(so) );
  DFD2 \U1/U3  ( .D(\U1/ffin ), .CP(update_clk), .Q(temp_out) );
endmodule


module Intro_Top_DW_bc_2 ( capture_clk, update_clk, capture_en, update_en, 
        shift_dr, mode, si, data_in, data_out, so );
  input capture_clk, update_clk, capture_en, update_en, shift_dr, mode, si,
         data_in;
  output data_out, so;
  wire   update_out, \U1/U1/ffin , \U1/ffin , net441, net440, net439;

  MUX2ND0 \*cell*605  ( .I0(data_in), .I1(update_out), .S(mode), .ZN(net439)
         );
  CKND0 \*cell*604  ( .CLK(si), .CN(net440) );
  CKND0 \*cell*603  ( .CLK(so), .CN(net441) );
  MUX3ND0 \*cell*602  ( .I0(net439), .I1(net440), .I2(net441), .S0(shift_dr), 
        .S1(capture_en), .ZN(\U1/U1/ffin ) );
  CKMUX2D0 \*cell*601  ( .I0(update_out), .I1(so), .S(update_en), .Z(\U1/ffin ) );
  CKND0 \*cell*600  ( .CLK(net439), .CN(data_out) );
  DFD2 \U1/U1/U3  ( .D(\U1/U1/ffin ), .CP(capture_clk), .Q(so) );
  DFD2 \U1/U3  ( .D(\U1/ffin ), .CP(update_clk), .Q(update_out) );
endmodule


module Intro_Top_DW_bc_2_test_2 ( capture_clk, update_clk, capture_en, 
        update_en, shift_dr, mode, si, data_in, data_out, so );
  input capture_clk, update_clk, capture_en, update_en, shift_dr, mode, si,
         data_in;
  output data_out, so;
  wire   update_out, \U1/U1/ffin , \U1/ffin , net441, net440, net439;

  MUX2ND0 \*cell*605  ( .I0(data_in), .I1(update_out), .S(mode), .ZN(net439)
         );
  CKND0 \*cell*604  ( .CLK(si), .CN(net440) );
  CKND0 \*cell*603  ( .CLK(so), .CN(net441) );
  MUX3ND0 \*cell*602  ( .I0(net439), .I1(net440), .I2(net441), .S0(shift_dr), 
        .S1(capture_en), .ZN(\U1/U1/ffin ) );
  CKMUX2D0 \*cell*601  ( .I0(update_out), .I1(so), .S(update_en), .Z(\U1/ffin ) );
  CKND0 \*cell*600  ( .CLK(net439), .CN(data_out) );
  DFD2 \U1/U1/U3  ( .D(\U1/U1/ffin ), .CP(capture_clk), .Q(so) );
  DFD2 \U1/U3  ( .D(\U1/ffin ), .CP(update_clk), .Q(update_out) );
endmodule


module Intro_Top_DW_bc_2_test_1 ( capture_clk, update_clk, capture_en, 
        update_en, shift_dr, mode, si, data_in, data_out, so );
  input capture_clk, update_clk, capture_en, update_en, shift_dr, mode, si,
         data_in;
  output data_out, so;
  wire   update_out, \U1/U1/ffin , \U1/ffin , net441, net440, net439;

  MUX2ND0 \*cell*605  ( .I0(data_in), .I1(update_out), .S(mode), .ZN(net439)
         );
  CKND0 \*cell*604  ( .CLK(si), .CN(net440) );
  CKND0 \*cell*603  ( .CLK(so), .CN(net441) );
  MUX3ND0 \*cell*602  ( .I0(net439), .I1(net440), .I2(net441), .S0(shift_dr), 
        .S1(capture_en), .ZN(\U1/U1/ffin ) );
  CKMUX2D0 \*cell*601  ( .I0(update_out), .I1(so), .S(update_en), .Z(\U1/ffin ) );
  CKND0 \*cell*600  ( .CLK(net439), .CN(data_out) );
  DFD2 \U1/U1/U3  ( .D(\U1/U1/ffin ), .CP(capture_clk), .Q(so) );
  DFD2 \U1/U3  ( .D(\U1/ffin ), .CP(update_clk), .Q(update_out) );
endmodule


module Intro_Top_DW_bc_2_test_0 ( capture_clk, update_clk, capture_en, 
        update_en, shift_dr, mode, si, data_in, data_out, so );
  input capture_clk, update_clk, capture_en, update_en, shift_dr, mode, si,
         data_in;
  output data_out, so;
  wire   update_out, \U1/U1/ffin , \U1/ffin , net441, net440, net439;

  MUX2ND0 \*cell*605  ( .I0(data_in), .I1(update_out), .S(mode), .ZN(net439)
         );
  CKND0 \*cell*604  ( .CLK(si), .CN(net440) );
  CKND0 \*cell*603  ( .CLK(so), .CN(net441) );
  MUX3ND0 \*cell*602  ( .I0(net439), .I1(net440), .I2(net441), .S0(shift_dr), 
        .S1(capture_en), .ZN(\U1/U1/ffin ) );
  CKMUX2D0 \*cell*601  ( .I0(update_out), .I1(so), .S(update_en), .Z(\U1/ffin ) );
  CKND0 \*cell*600  ( .CLK(net439), .CN(data_out) );
  DFD2 \U1/U1/U3  ( .D(\U1/U1/ffin ), .CP(capture_clk), .Q(so) );
  DFD2 \U1/U3  ( .D(\U1/ffin ), .CP(update_clk), .Q(update_out) );
endmodule



    module Intro_Top_DW_tap_uc_width2_id0_idcode_opcode1_version0_part0_man_num0_sync_mode1 ( 
        tck, trst_n, tms, tdi, so, bypass_sel, sentinel_val, device_id_sel, 
        user_code_sel, user_code_val, ver, ver_sel, part_num, part_num_sel, 
        mnfr_id, mnfr_id_sel, clock_dr, shift_dr, update_dr, tdo, tdo_en, 
        tap_state, instructions, sync_capture_en, sync_update_dr, test );
  input [0:0] sentinel_val;
  input [31:0] user_code_val;
  input [3:0] ver;
  input [15:0] part_num;
  input [10:0] mnfr_id;
  output [15:0] tap_state;
  output [1:0] instructions;
  input tck, trst_n, tms, tdi, so, bypass_sel, device_id_sel, user_code_sel,
         ver_sel, part_num_sel, mnfr_id_sel, test;
  output clock_dr, shift_dr, update_dr, tdo, tdo_en, sync_capture_en,
         sync_update_dr;
  wire   tck_n, dr_sel_int, shift_ir_int, instr_rst, instr_so, byp_so,
         tdo_ffin, \U6/ffin , \U5/U1_1/ffin , \U5/U1_0/ffin , \U5/ff_d[1] ,
         \U5/ff_d[0] , \U5/ff_q[1] , \U5/ff_q[0] , \U5/temp_so[1] , \U5/rst_n ,
         \U1/int_tck_n , \U1/reset , \U1/sel_cap_dr , \U1/dr_sel_int_next ,
         \U1/next_state[0] , \U1/next_state[1] , \U1/next_state[2] ,
         \U1/next_state[3] , \U1/next_state[4] , \U1/next_state[5] ,
         \U1/next_state[6] , \U1/next_state[7] , \U1/next_state[8] ,
         \U1/next_state[9] , \U1/next_state[10] , \U1/next_state[11] ,
         \U1/next_state[12] , \U1/next_state[13] , \U1/next_state[14] ,
         \U1/next_state[15] , net396, net395, net394, net393, net392, net391,
         net390, net389, net388, net387, net386, net385, net384, net383,
         net382, net381, net380, net379, net378, net377, net376, net375,
         net374, net373, net372, net371, net370, net369, net368, net367,
         net366, net365, net364, net363, net362, net361, net360, net359,
         net358, net357, net356, net355, net354, net353, net352, net351,
         net350, net349, net348, net347, net346, net345, net344, net343,
         net342, net341, net340, net339, net338, net337, net336, net335,
         net334, net333, net332, net331, net330, net329, net328, net327,
         net326, net325, net324, net323, net322, net321, net320, net319,
         net318, net317, net316, net315, net314, net313, net312, net311,
         net310, net309, net308, net307, net306, net305, net304, net303,
         net302, net301, net300, net299, net298, net297, net296, net295,
         net294, net293, net292, net291, net290, net413;
  assign sync_update_dr = net413;

  NR2XD0 \U1/U1  ( .A1(tap_state[3]), .A2(tap_state[4]), .ZN(\U1/sel_cap_dr )
         );
  OR2D1 \U1/U3  ( .A1(tck), .A2(\U1/sel_cap_dr ), .Z(clock_dr) );
  IND2D0 \U1/U10  ( .A1(\U1/reset ), .B1(trst_n), .ZN(instr_rst) );
  CKND0 \U1/U11  ( .CLK(tck), .CN(\U1/int_tck_n ) );
  OR2D1 \*cell*539  ( .A1(tap_state[7]), .A2(tap_state[8]), .Z(net342) );
  OR2D1 \*cell*538  ( .A1(tap_state[9]), .A2(tap_state[6]), .Z(net396) );
  OR2D1 \*cell*537  ( .A1(net342), .A2(net396), .Z(net352) );
  OR2D1 \*cell*536  ( .A1(tap_state[5]), .A2(tap_state[3]), .Z(net395) );
  OR2D1 \*cell*535  ( .A1(net352), .A2(net395), .Z(net373) );
  CKND0 \*cell*534  ( .CLK(net373), .CN(net388) );
  CKND0 \*cell*533  ( .CLK(tap_state[2]), .CN(net394) );
  NR2XD0 \*cell*532  ( .A1(tap_state[4]), .A2(net394), .ZN(net389) );
  OR2D1 \*cell*531  ( .A1(tap_state[10]), .A2(tap_state[11]), .Z(net306) );
  CKND0 \*cell*530  ( .CLK(tap_state[0]), .CN(net371) );
  CKND0 \*cell*529  ( .CLK(tap_state[12]), .CN(net367) );
  OR2D1 \*cell*528  ( .A1(tap_state[13]), .A2(tap_state[14]), .Z(net354) );
  OR2D1 \*cell*527  ( .A1(tap_state[1]), .A2(tap_state[15]), .Z(net393) );
  OR2D1 \*cell*526  ( .A1(net354), .A2(net393), .Z(net392) );
  CKND0 \*cell*525  ( .CLK(net392), .CN(net335) );
  ND3D1 \*cell*524  ( .A1(net371), .A2(net367), .A3(net335), .ZN(net391) );
  CKND0 \*cell*523  ( .CLK(net391), .CN(net346) );
  IND2D0 \*cell*522  ( .A1(net306), .B1(net346), .ZN(net386) );
  CKND0 \*cell*521  ( .CLK(net386), .CN(net390) );
  ND3D1 \*cell*520  ( .A1(net388), .A2(net389), .A3(net390), .ZN(net387) );
  CKND0 \*cell*519  ( .CLK(net387), .CN(net308) );
  IND2D0 \*cell*518  ( .A1(tms), .B1(net308), .ZN(net316) );
  NR2XD0 \*cell*517  ( .A1(tap_state[8]), .A2(tap_state[6]), .ZN(net382) );
  CKND0 \*cell*516  ( .CLK(tap_state[3]), .CN(net297) );
  CKND0 \*cell*514  ( .CLK(tap_state[4]), .CN(net380) );
  OR2D1 \*cell*512  ( .A1(tap_state[2]), .A2(net386), .Z(net385) );
  CKND0 \*cell*511  ( .CLK(net385), .CN(net350) );
  ND3D1 \*cell*510  ( .A1(net380), .A2(net351), .A3(net350), .ZN(net384) );
  CKND0 \*cell*509  ( .CLK(net384), .CN(net333) );
  ND3D1 \*cell*508  ( .A1(net297), .A2(net334), .A3(net333), .ZN(net383) );
  CKND0 \*cell*507  ( .CLK(net383), .CN(net341) );
  ND3D1 \*cell*506  ( .A1(tap_state[7]), .A2(net382), .A3(net341), .ZN(net381)
         );
  CKND0 \*cell*505  ( .CLK(net381), .CN(net310) );
  NR2XD0 \*cell*504  ( .A1(net352), .A2(net297), .ZN(net377) );
  OR2D1 \*cell*503  ( .A1(net373), .A2(net380), .Z(net379) );
  IND2D0 \*cell*502  ( .A1(net379), .B1(net350), .ZN(net378) );
  IOA21D2 \*cell*501  ( .A1(net377), .A2(net333), .B(net378), .ZN(net375) );
  CKND0 \*cell*500  ( .CLK(tms), .CN(net314) );
  OAI21D1 \*cell*499  ( .A1(net310), .A2(net375), .B(net314), .ZN(net376) );
  CKND0 \*cell*498  ( .CLK(net376), .CN(\U1/next_state[4] ) );
  INR2D1 \*cell*497  ( .A1(net316), .B1(\U1/next_state[4] ), .ZN(
        \U1/dr_sel_int_next ) );
  CKND0 \*cell*496  ( .CLK(net375), .CN(net315) );
  NR2XD0 \*cell*495  ( .A1(tap_state[1]), .A2(tap_state[14]), .ZN(net369) );
  CKND0 \*cell*494  ( .CLK(tap_state[15]), .CN(net363) );
  OR2D1 \*cell*493  ( .A1(tap_state[4]), .A2(tap_state[2]), .Z(net374) );
  OR2D1 \*cell*492  ( .A1(net373), .A2(net374), .Z(net343) );
  OR2D1 \*cell*491  ( .A1(tap_state[12]), .A2(net306), .Z(net372) );
  OR2D1 \*cell*490  ( .A1(net343), .A2(net372), .Z(net362) );
  CKND0 \*cell*489  ( .CLK(net362), .CN(net336) );
  ND3D1 \*cell*488  ( .A1(net371), .A2(net363), .A3(net336), .ZN(net370) );
  CKND0 \*cell*487  ( .CLK(net370), .CN(net360) );
  ND3D1 \*cell*486  ( .A1(tap_state[13]), .A2(net369), .A3(net360), .ZN(net323) );
  NR2XD0 \*cell*485  ( .A1(tap_state[1]), .A2(tap_state[13]), .ZN(net368) );
  ND3D1 \*cell*484  ( .A1(tap_state[14]), .A2(net368), .A3(net360), .ZN(net326) );
  NR2XD0 \*cell*483  ( .A1(tap_state[0]), .A2(net367), .ZN(net365) );
  CKND0 \*cell*482  ( .CLK(net306), .CN(net366) );
  ND3D1 \*cell*481  ( .A1(net365), .A2(net366), .A3(net335), .ZN(net364) );
  OR2D1 \*cell*480  ( .A1(net343), .A2(net364), .Z(net322) );
  AN4XD1 \*cell*479  ( .A1(net315), .A2(net323), .A3(net326), .A4(net322), .Z(
        net337) );
  NR2XD0 \*cell*478  ( .A1(tap_state[0]), .A2(net363), .ZN(net361) );
  INR2D1 \*cell*477  ( .A1(net361), .B1(net362), .ZN(net359) );
  MUX2ND0 \*cell*476  ( .I0(net359), .I1(net360), .S(tap_state[1]), .ZN(net355) );
  NR2XD0 \*cell*474  ( .A1(tap_state[7]), .A2(tap_state[6]), .ZN(net358) );
  IND2D0 \*cell*473  ( .A1(net291), .B1(net358), .ZN(net357) );
  IND2D0 \*cell*472  ( .A1(net357), .B1(net341), .ZN(net356) );
  OAI21D1 \*cell*471  ( .A1(net354), .A2(net355), .B(net356), .ZN(net353) );
  CKND0 \*cell*470  ( .CLK(net353), .CN(net317) );
  CKND0 \*cell*469  ( .CLK(net352), .CN(net348) );
  NR3D0 \*cell*468  ( .A1(net351), .A2(tap_state[4]), .A3(tap_state[3]), .ZN(
        net349) );
  ND3D1 \*cell*467  ( .A1(net348), .A2(net349), .A3(net350), .ZN(net347) );
  CKND0 \*cell*466  ( .CLK(net347), .CN(net311) );
  XNR2D2 \*cell*465  ( .A1(tap_state[11]), .A2(tap_state[10]), .ZN(net345) );
  IND2D0 \*cell*464  ( .A1(net345), .B1(net346), .ZN(net344) );
  OR2D1 \*cell*463  ( .A1(net343), .A2(net344), .Z(net324) );
  CKND0 \*cell*462  ( .CLK(net324), .CN(net325) );
  NR3D0 \*cell*461  ( .A1(net311), .A2(net325), .A3(net308), .ZN(net339) );
  CKND0 \*cell*460  ( .CLK(net342), .CN(net331) );
  ND3D1 \*cell*459  ( .A1(tap_state[6]), .A2(net331), .A3(net341), .ZN(net340)
         );
  CKND0 \*cell*458  ( .CLK(net340), .CN(net312) );
  INR3D0 \*cell*457  ( .A1(net339), .B1(net310), .B2(net312), .ZN(net338) );
  ND3D1 \*cell*456  ( .A1(net337), .A2(net317), .A3(net338), .ZN(net328) );
  ND3D1 \*cell*455  ( .A1(tap_state[0]), .A2(net335), .A3(net336), .ZN(net318)
         );
  NR3D0 \*cell*454  ( .A1(net334), .A2(tap_state[6]), .A3(tap_state[3]), .ZN(
        net332) );
  ND3D1 \*cell*453  ( .A1(net331), .A2(net332), .A3(net333), .ZN(net327) );
  CKND0 \*cell*452  ( .CLK(net327), .CN(net330) );
  INR2D1 \*cell*451  ( .A1(net318), .B1(net330), .ZN(net329) );
  MUX2ND0 \*cell*450  ( .I0(net314), .I1(net328), .S(net329), .ZN(
        \U1/next_state[0] ) );
  NR2XD0 \*cell*449  ( .A1(tms), .A2(net327), .ZN(\U1/next_state[10] ) );
  CKND0 \*cell*448  ( .CLK(net326), .CN(net319) );
  OA21D1 \*cell*447  ( .A1(net325), .A2(net319), .B(net314), .Z(
        \U1/next_state[11] ) );
  INR2D1 \*cell*446  ( .A1(tms), .B1(net324), .ZN(\U1/next_state[12] ) );
  CKND0 \*cell*445  ( .CLK(net323), .CN(net321) );
  CKND0 \*cell*444  ( .CLK(net322), .CN(net320) );
  OA21D1 \*cell*443  ( .A1(net321), .A2(net320), .B(net314), .Z(
        \U1/next_state[13] ) );
  AN2XD1 \*cell*442  ( .A1(net321), .A2(tms), .Z(\U1/next_state[14] ) );
  OA21D1 \*cell*441  ( .A1(net319), .A2(net320), .B(tms), .Z(
        \U1/next_state[15] ) );
  AOI21D1 \*cell*440  ( .A1(net317), .A2(net318), .B(tms), .ZN(
        \U1/next_state[1] ) );
  NR2XD0 \*cell*439  ( .A1(net317), .A2(net314), .ZN(\U1/next_state[2] ) );
  CKND0 \*cell*438  ( .CLK(net316), .CN(\U1/next_state[3] ) );
  NR2XD0 \*cell*437  ( .A1(net315), .A2(net314), .ZN(\U1/next_state[5] ) );
  OAI21D1 \*cell*436  ( .A1(net312), .A2(net311), .B(net314), .ZN(net313) );
  CKND0 \*cell*435  ( .CLK(net313), .CN(\U1/next_state[6] ) );
  AN2XD1 \*cell*434  ( .A1(net312), .A2(tms), .Z(\U1/next_state[7] ) );
  OAI21D1 \*cell*433  ( .A1(net310), .A2(net311), .B(tms), .ZN(net309) );
  CKND0 \*cell*432  ( .CLK(net309), .CN(\U1/next_state[8] ) );
  AN2XD1 \*cell*431  ( .A1(tms), .A2(net308), .Z(\U1/next_state[9] ) );
  XOR2D2 \*cell*430  ( .A1(test), .A2(\U1/int_tck_n ), .Z(tck_n) );
  CKND0 \*cell*429  ( .CLK(shift_ir_int), .CN(net307) );
  NR2XD0 \*cell*428  ( .A1(\U5/temp_so[1] ), .A2(net307), .ZN(net304) );
  CKND0 \*cell*427  ( .CLK(instr_so), .CN(net294) );
  OR2D1 \*cell*426  ( .A1(shift_ir_int), .A2(net306), .Z(net301) );
  CKND0 \*cell*425  ( .CLK(net301), .CN(net305) );
  MUX2ND0 \*cell*424  ( .I0(net304), .I1(net294), .S(net305), .ZN(
        \U5/U1_0/ffin ) );
  CKND0 \*cell*423  ( .CLK(\U5/temp_so[1] ), .CN(net302) );
  CKND2D0 \*cell*422  ( .A1(shift_ir_int), .A2(tdi), .ZN(net303) );
  OAI21D1 \*cell*421  ( .A1(net301), .A2(net302), .B(net303), .ZN(
        \U5/U1_1/ffin ) );
  MUX2ND0 \*cell*420  ( .I0(instructions[0]), .I1(instr_so), .S(tap_state[15]), 
        .ZN(\U5/ff_d[0] ) );
  MUX2ND0 \*cell*419  ( .I0(instructions[1]), .I1(\U5/temp_so[1] ), .S(
        tap_state[15]), .ZN(\U5/ff_d[1] ) );
  CKND0 \*cell*418  ( .CLK(instr_rst), .CN(net300) );
  CKMUX2D0 \*cell*417  ( .I0(net300), .I1(trst_n), .S(test), .Z(\U5/rst_n ) );
  AN2XD1 \*cell*416  ( .A1(tdi), .A2(shift_dr), .Z(net299) );
  MUX2ND0 \*cell*415  ( .I0(net299), .I1(byp_so), .S(dr_sel_int), .ZN(net298)
         );
  INR2D1 \*cell*414  ( .A1(net297), .B1(net298), .ZN(\U6/ffin ) );
  NR3D0 \*cell*413  ( .A1(tap_state[3]), .A2(tap_state[4]), .A3(shift_dr), 
        .ZN(sync_capture_en) );
  NR2XD0 \*cell*412  ( .A1(shift_dr), .A2(shift_ir_int), .ZN(net296) );
  CKND0 \*cell*411  ( .CLK(net296), .CN(tdo_en) );
  CKND0 \*cell*410  ( .CLK(byp_so), .CN(net292) );
  CKND0 \*cell*409  ( .CLK(so), .CN(net293) );
  AOI21D1 \*cell*408  ( .A1(instructions[0]), .A2(instructions[1]), .B(
        bypass_sel), .ZN(net295) );
  MUX3ND0 \*cell*407  ( .I0(net292), .I1(net293), .I2(net294), .S0(net295), 
        .S1(tap_state[11]), .ZN(tdo_ffin) );
  CKND0 \*cell*406  ( .CLK(tck_n), .CN(net290) );
  NR2XD0 \*cell*405  ( .A1(net290), .A2(net291), .ZN(update_dr) );
  DFCNQD2 \U1/current_state_reg[15]  ( .D(\U1/next_state[15] ), .CP(tck), 
        .CDN(trst_n), .Q(tap_state[15]) );
  DFCNQD2 \U1/current_state_reg[14]  ( .D(\U1/next_state[14] ), .CP(tck), 
        .CDN(trst_n), .Q(tap_state[14]) );
  DFSNQD2 \U1/current_state_reg[0]  ( .D(\U1/next_state[0] ), .CP(tck), .SDN(
        trst_n), .Q(tap_state[0]) );
  DFCNQD2 \U1/current_state_reg[1]  ( .D(\U1/next_state[1] ), .CP(tck), .CDN(
        trst_n), .Q(tap_state[1]) );
  DFCNQD2 \U1/current_state_reg[2]  ( .D(\U1/next_state[2] ), .CP(tck), .CDN(
        trst_n), .Q(tap_state[2]) );
  DFCNQD2 \U1/current_state_reg[13]  ( .D(\U1/next_state[13] ), .CP(tck), 
        .CDN(trst_n), .Q(tap_state[13]) );
  DFCNQD2 \U1/current_state_reg[11]  ( .D(\U1/next_state[11] ), .CP(tck), 
        .CDN(trst_n), .Q(tap_state[11]) );
  DFCNQD2 \U1/current_state_reg[12]  ( .D(\U1/next_state[12] ), .CP(tck), 
        .CDN(trst_n), .Q(tap_state[12]) );
  DFCND2 \U1/current_state_reg[9]  ( .D(\U1/next_state[9] ), .CP(tck), .CDN(
        trst_n), .Q(tap_state[9]), .QN(net334) );
  DFCNQD2 \U1/current_state_reg[3]  ( .D(\U1/next_state[3] ), .CP(tck), .CDN(
        trst_n), .Q(tap_state[3]) );
  DFCNQD2 \U1/current_state_reg[6]  ( .D(\U1/next_state[6] ), .CP(tck), .CDN(
        trst_n), .Q(tap_state[6]) );
  DFCNQD2 \U1/current_state_reg[7]  ( .D(\U1/next_state[7] ), .CP(tck), .CDN(
        trst_n), .Q(tap_state[7]) );
  DFCND2 \U1/current_state_reg[8]  ( .D(\U1/next_state[8] ), .CP(tck), .CDN(
        trst_n), .Q(tap_state[8]), .QN(net291) );
  DFCNQD2 \U1/current_state_reg[4]  ( .D(\U1/next_state[4] ), .CP(tck), .CDN(
        trst_n), .Q(tap_state[4]) );
  DFCND2 \U1/current_state_reg[5]  ( .D(\U1/next_state[5] ), .CP(tck), .CDN(
        trst_n), .Q(tap_state[5]), .QN(net351) );
  DFCNQD2 \U1/current_state_reg[10]  ( .D(\U1/next_state[10] ), .CP(tck), 
        .CDN(trst_n), .Q(tap_state[10]) );
  DFCNQD2 \U1/dr_sel_int_reg  ( .D(\U1/dr_sel_int_next ), .CP(tck), .CDN(
        trst_n), .Q(dr_sel_int) );
  DFD1 U8 ( .D(tdo_ffin), .CP(tck_n), .Q(tdo) );
  DFD1 \U6/U4  ( .D(\U6/ffin ), .CP(tck), .Q(byp_so) );
  DFD1 \U5/U1_1/U3  ( .D(\U5/U1_1/ffin ), .CP(tck), .Q(\U5/temp_so[1] ) );
  DFD1 \U5/U1_0/U3  ( .D(\U5/U1_0/ffin ), .CP(tck), .Q(instr_so) );
  DFCND2 \U5/U3_1  ( .D(\U5/ff_d[1] ), .CP(tck_n), .CDN(\U5/rst_n ), .Q(
        \U5/ff_q[1] ), .QN(instructions[1]) );
  DFCND2 \U5/U3_0  ( .D(\U5/ff_d[0] ), .CP(tck_n), .CDN(\U5/rst_n ), .Q(
        \U5/ff_q[0] ), .QN(instructions[0]) );
  DFD1 \U1/U9  ( .D(tap_state[0]), .CP(tck_n), .Q(\U1/reset ) );
  DFCND2 \U1/U8  ( .D(tap_state[11]), .CP(tck_n), .CDN(trst_n), .Q(
        shift_ir_int) );
  DFCND2 \U1/U7  ( .D(tap_state[4]), .CP(tck_n), .CDN(trst_n), .Q(shift_dr) );
  BUFFD16 \*cell*586  ( .I(tap_state[8]), .Z(net413) );
endmodule


module XorNor ( X, Y, A, B, C );
  input A, B, C;
  output X, Y;


  NR2D0 U1 ( .A1(C), .A2(X), .ZN(Y) );
  CKXOR2D0 U2 ( .A1(B), .A2(A), .Z(X) );
endmodule


module SR ( Q, Qn, S, R );
  input S, R;
  output Q, Qn;


  CKND2D2 U2 ( .A1(Q), .A2(R), .ZN(Qn) );
  CKND2D0 U1 ( .A1(S), .A2(Qn), .ZN(Q) );
endmodule


module AndOr ( X, Y, A, B, C );
  input A, B, C;
  output X, Y;


  OR2D0 U1 ( .A1(C), .A2(B), .Z(Y) );
  AN2D0 U2 ( .A1(B), .A2(A), .Z(X) );
endmodule

