
module PLL ( ClockOut, ClockIn, Reset );
  input ClockIn, Reset;
  output ClockOut;
  wire   n5, CkInWire, n2, n3, n4;
  wire   [1:0] AdjFreq;

  DEL005 CkInDelay1 ( .I(ClockIn), .Z(CkInWire) );
  Comparator Comp1 ( .AdjustFreq(AdjFreq), .ClockIn(ClockIn), .PLLClock(n4), 
        .Reset(Reset) );
  VFO VFO1 ( .ClockOut(n5), .AdjustFreq(AdjFreq), .ClockIn(CkInWire), .Reset(
        Reset) );
  CKND16 U1 ( .CLK(n2), .CN(n3) );
  CKND16 U2 ( .CLK(n2), .CN(ClockOut) );
  CKND0 U3 ( .CLK(n5), .CN(n2) );
  BUFFD0 U4 ( .I(n3), .Z(n4) );
endmodule


module VFO ( ClockOut, AdjustFreq, ClockIn, Reset );
  input [1:0] AdjustFreq;
  input ClockIn, Reset;
  output ClockOut;
  wire   FastClock, N10, N11, N12, N13, N15, N16, N17, N18, N19, N27, N28, N29,
         N30, N31, N35, N36, N37, N38, n12, n14, n15, n16, n17, n18,
         \add_159/carry[4] , \add_159/carry[3] , \add_159/carry[2] ,
         \add_140/carry[4] , \add_140/carry[3] , \add_140/carry[2] , n1, n2,
         n3, n4, n5, n6, n7, n8, n9, n10, n11, n13, n19, n20, n21, n22, n23,
         n24, n25, n26, n27, n28, n29, n30;
  wire   [3:0] WireD;
  wire   [4:0] ProgClk;
  wire   [4:0] DivideFactor;

  DEL005 \DelayLine[0].Delay85ps  ( .I(WireD[0]), .Z(WireD[1]) );
  DEL005 \DelayLine[1].Delay85ps  ( .I(WireD[1]), .Z(WireD[2]) );
  DEL005 \DelayLine[2].Delay85ps  ( .I(WireD[2]), .Z(WireD[3]) );
  INVD0 Inv75ps ( .I(FastClock), .ZN(WireD[0]) );
  INR2XD1 U23 ( .A1(WireD[3]), .B1(Reset), .ZN(FastClock) );
  DFCNQD1 \ProgClk_reg[4]  ( .D(N19), .CP(FastClock), .CDN(n30), .Q(ProgClk[4]) );
  DFCNQD1 \ProgClk_reg[2]  ( .D(N17), .CP(FastClock), .CDN(n30), .Q(ProgClk[2]) );
  DFCNQD1 \ProgClk_reg[3]  ( .D(N18), .CP(FastClock), .CDN(n30), .Q(ProgClk[3]) );
  DFCNQD1 \ProgClk_reg[1]  ( .D(N16), .CP(FastClock), .CDN(n30), .Q(ProgClk[1]) );
  DFCNQD1 \ProgClk_reg[0]  ( .D(N15), .CP(FastClock), .CDN(n30), .Q(ProgClk[0]) );
  DFCNQD1 \DivideFactor_reg[3]  ( .D(n14), .CP(ClockIn), .CDN(n30), .Q(
        DivideFactor[3]) );
  DFCNQD1 \DivideFactor_reg[2]  ( .D(n15), .CP(ClockIn), .CDN(n30), .Q(
        DivideFactor[2]) );
  DFCNQD1 \DivideFactor_reg[0]  ( .D(n18), .CP(ClockIn), .CDN(n30), .Q(
        DivideFactor[0]) );
  DFCNQD1 \DivideFactor_reg[1]  ( .D(n16), .CP(ClockIn), .CDN(n30), .Q(
        DivideFactor[1]) );
  DFSND1 \DivideFactor_reg[4]  ( .D(n17), .CP(ClockIn), .SDN(n1), .Q(
        DivideFactor[4]), .QN(n20) );
  DFCNQD2 ClockOutReg_reg ( .D(n12), .CP(FastClock), .CDN(n30), .Q(ClockOut)
         );
  OAI31D0 U3 ( .A1(n19), .A2(n21), .A3(n20), .B(n9), .ZN(n10) );
  INR2D1 U4 ( .A1(n22), .B1(ProgClk[0]), .ZN(N15) );
  INVD1 U5 ( .I(Reset), .ZN(n1) );
  INVD0 U6 ( .I(DivideFactor[0]), .ZN(N27) );
  INVD0 U7 ( .I(DivideFactor[2]), .ZN(n5) );
  MUX2D1 U8 ( .I0(n10), .I1(n11), .S(AdjustFreq[1]), .Z(n8) );
  AO222D1 U9 ( .A1(N31), .A2(n6), .B1(N38), .B2(n7), .C1(DivideFactor[4]), 
        .C2(n8), .Z(n17) );
  NR2D1 U10 ( .A1(n8), .A2(n9), .ZN(n7) );
  HA1D0 U11 ( .A(DivideFactor[1]), .B(DivideFactor[0]), .CO(\add_159/carry[2] ), .S(N28) );
  HA1D0 U12 ( .A(DivideFactor[2]), .B(\add_159/carry[2] ), .CO(
        \add_159/carry[3] ), .S(N29) );
  HA1D0 U13 ( .A(DivideFactor[3]), .B(\add_159/carry[3] ), .CO(
        \add_159/carry[4] ), .S(N30) );
  HA1D0 U14 ( .A(ProgClk[1]), .B(ProgClk[0]), .CO(\add_140/carry[2] ), .S(N10)
         );
  HA1D0 U15 ( .A(ProgClk[2]), .B(\add_140/carry[2] ), .CO(\add_140/carry[3] ), 
        .S(N11) );
  HA1D0 U16 ( .A(ProgClk[3]), .B(\add_140/carry[3] ), .CO(\add_140/carry[4] ), 
        .S(N12) );
  CKXOR2D0 U17 ( .A1(\add_140/carry[4] ), .A2(ProgClk[4]), .Z(N13) );
  CKXOR2D0 U18 ( .A1(\add_159/carry[4] ), .A2(DivideFactor[4]), .Z(N31) );
  NR2D0 U19 ( .A1(DivideFactor[1]), .A2(DivideFactor[0]), .ZN(n2) );
  AO21D0 U20 ( .A1(DivideFactor[0]), .A2(DivideFactor[1]), .B(n2), .Z(N35) );
  CKND2D0 U21 ( .A1(n2), .A2(n5), .ZN(n3) );
  OAI21D0 U22 ( .A1(n2), .A2(n5), .B(n3), .ZN(N36) );
  XNR2D0 U24 ( .A1(n3), .A2(DivideFactor[3]), .ZN(N37) );
  NR2D0 U25 ( .A1(DivideFactor[3]), .A2(n3), .ZN(n4) );
  CKXOR2D0 U26 ( .A1(DivideFactor[4]), .A2(n4), .Z(N38) );
  CKND0 U27 ( .CLK(Reset), .CN(n30) );
  AO222D0 U28 ( .A1(N27), .A2(n6), .B1(N27), .B2(n7), .C1(DivideFactor[0]), 
        .C2(n8), .Z(n18) );
  AO222D0 U29 ( .A1(N28), .A2(n6), .B1(N35), .B2(n7), .C1(DivideFactor[1]), 
        .C2(n8), .Z(n16) );
  AO222D0 U30 ( .A1(N29), .A2(n6), .B1(N36), .B2(n7), .C1(DivideFactor[2]), 
        .C2(n8), .Z(n15) );
  AO222D0 U31 ( .A1(N30), .A2(n6), .B1(N37), .B2(n7), .C1(DivideFactor[3]), 
        .C2(n8), .Z(n14) );
  NR2D0 U32 ( .A1(n8), .A2(AdjustFreq[0]), .ZN(n6) );
  OAI31D0 U33 ( .A1(n13), .A2(DivideFactor[1]), .A3(DivideFactor[0]), .B(
        AdjustFreq[0]), .ZN(n11) );
  ND3D0 U34 ( .A1(n19), .A2(n20), .A3(n5), .ZN(n13) );
  CKND0 U35 ( .CLK(AdjustFreq[0]), .CN(n9) );
  ND3D0 U36 ( .A1(DivideFactor[1]), .A2(DivideFactor[0]), .A3(DivideFactor[2]), 
        .ZN(n21) );
  XNR2D0 U37 ( .A1(ClockOut), .A2(n22), .ZN(n12) );
  AN2D0 U38 ( .A1(N13), .A2(n22), .Z(N19) );
  AN2D0 U39 ( .A1(N12), .A2(n22), .Z(N18) );
  AN2D0 U40 ( .A1(N11), .A2(n22), .Z(N17) );
  AN2D0 U41 ( .A1(N10), .A2(n22), .Z(N16) );
  OAI21D0 U42 ( .A1(ProgClk[4]), .A2(n20), .B(n23), .ZN(n22) );
  AO221D0 U43 ( .A1(n19), .A2(ProgClk[3]), .B1(n20), .B2(ProgClk[4]), .C(n24), 
        .Z(n23) );
  OA222D0 U44 ( .A1(n25), .A2(n5), .B1(ProgClk[2]), .B2(n26), .C1(ProgClk[3]), 
        .C2(n19), .Z(n24) );
  NR2D0 U45 ( .A1(DivideFactor[2]), .A2(n27), .ZN(n26) );
  CKND0 U46 ( .CLK(n27), .CN(n25) );
  OAI32D0 U47 ( .A1(N27), .A2(ProgClk[0]), .A3(n28), .B1(ProgClk[1]), .B2(n29), 
        .ZN(n27) );
  CKND0 U48 ( .CLK(DivideFactor[1]), .CN(n29) );
  INR2D0 U49 ( .A1(ProgClk[1]), .B1(DivideFactor[1]), .ZN(n28) );
  CKND0 U50 ( .CLK(DivideFactor[3]), .CN(n19) );
endmodule


module Comparator ( AdjustFreq, ClockIn, PLLClock, Reset );
  output [1:0] AdjustFreq;
  input ClockIn, PLLClock, Reset;
  wire   N6, N8, N37, N38, N39, n6, n7, n8, n2, n3, n4, n5, n9;
  wire   [1:0] ClockInN;
  wire   [1:0] PLLClockN;

  MOAI22D1 U5 ( .A1(N8), .A2(n6), .B1(n7), .B2(ClockInN[1]), .ZN(N38) );
  MOAI22D1 U8 ( .A1(PLLClockN[1]), .A2(n8), .B1(n7), .B2(N39), .ZN(N37) );
  DFSNQD1 \AdjustFreq_reg[0]  ( .D(N37), .CP(PLLClock), .SDN(n9), .Q(
        AdjustFreq[0]) );
  DFCNQD1 \AdjustFreq_reg[1]  ( .D(N38), .CP(PLLClock), .CDN(n9), .Q(
        AdjustFreq[1]) );
  DFCNQD1 \PLLClockN_reg[0]  ( .D(n5), .CP(PLLClock), .CDN(n2), .Q(
        PLLClockN[0]) );
  DFCNQD1 \PLLClockN_reg[1]  ( .D(N8), .CP(PLLClock), .CDN(n2), .Q(
        PLLClockN[1]) );
  DFCNQD1 \ClockInN_reg[1]  ( .D(N6), .CP(ClockIn), .CDN(n2), .Q(ClockInN[1])
         );
  DFCNQD1 \ClockInN_reg[0]  ( .D(n3), .CP(ClockIn), .CDN(n2), .Q(ClockInN[0])
         );
  DFSND1 ZeroCounters_reg ( .D(N39), .CP(ClockIn), .SDN(n9), .QN(n2) );
  NR2D1 U3 ( .A1(n4), .A2(n3), .ZN(N39) );
  XOR2D1 U4 ( .A1(n3), .A2(n4), .Z(N6) );
  INVD1 U6 ( .I(ClockInN[0]), .ZN(n3) );
  INVD1 U7 ( .I(ClockInN[1]), .ZN(n4) );
  INVD1 U9 ( .I(Reset), .ZN(n9) );
  AOI21D1 U10 ( .A1(ClockInN[0]), .A2(n7), .B(N39), .ZN(n6) );
  NR2D1 U11 ( .A1(n5), .A2(N6), .ZN(n8) );
  ND2D1 U12 ( .A1(PLLClockN[1]), .A2(PLLClockN[0]), .ZN(n7) );
  INVD1 U13 ( .I(PLLClockN[0]), .ZN(n5) );
  XNR2D1 U14 ( .A1(n5), .A2(PLLClockN[1]), .ZN(N8) );
endmodule

