
module ArrayIxedBus ( DBusBuf, DBus, QEna, Rst, Clk );
  output [7:0] DBusBuf;
  input [7:0] DBus;
  input [7:0] QEna;
  input Rst, Clk;
  wire   n1, n2, n3, n4, n5, n6, n7, n8;
  wire   [7:0] QWire;

  DFFa_7 \FF[0]  ( .Q(QWire[0]), .D(DBus[0]), .Clr(Rst), .Clk(Clk) );
  DFFa_6 \FF[1]  ( .Q(QWire[1]), .D(DBus[1]), .Clr(Rst), .Clk(Clk) );
  DFFa_5 \FF[2]  ( .Q(QWire[2]), .D(DBus[2]), .Clr(Rst), .Clk(Clk) );
  DFFa_4 \FF[3]  ( .Q(QWire[3]), .D(DBus[3]), .Clr(Rst), .Clk(Clk) );
  DFFa_3 \FF[4]  ( .Q(QWire[4]), .D(DBus[4]), .Clr(Rst), .Clk(Clk) );
  DFFa_2 \FF[5]  ( .Q(QWire[5]), .D(DBus[5]), .Clr(Rst), .Clk(Clk) );
  DFFa_1 \FF[6]  ( .Q(QWire[6]), .D(DBus[6]), .Clr(Rst), .Clk(Clk) );
  DFFa_0 \FF[7]  ( .Q(QWire[7]), .D(DBus[7]), .Clr(Rst), .Clk(Clk) );
  CKND0 U1 ( .CLK(QWire[7]), .CN(n8) );
  CKND0 U2 ( .CLK(QWire[6]), .CN(n7) );
  CKND0 U3 ( .CLK(QWire[5]), .CN(n6) );
  CKND0 U4 ( .CLK(QWire[4]), .CN(n5) );
  CKND0 U5 ( .CLK(QWire[3]), .CN(n4) );
  CKND0 U6 ( .CLK(QWire[2]), .CN(n3) );
  CKND0 U7 ( .CLK(QWire[1]), .CN(n2) );
  CKND0 U8 ( .CLK(QWire[0]), .CN(n1) );
  BUFTD16 \Nuf[7]  ( .I(n8), .OE(QEna[7]), .Z(DBusBuf[7]) );
  BUFTD16 \Nuf[6]  ( .I(n7), .OE(QEna[6]), .Z(DBusBuf[6]) );
  BUFTD16 \Nuf[5]  ( .I(n6), .OE(QEna[5]), .Z(DBusBuf[5]) );
  BUFTD16 \Nuf[4]  ( .I(n5), .OE(QEna[4]), .Z(DBusBuf[4]) );
  BUFTD16 \Nuf[3]  ( .I(n4), .OE(QEna[3]), .Z(DBusBuf[3]) );
  BUFTD16 \Nuf[2]  ( .I(n3), .OE(QEna[2]), .Z(DBusBuf[2]) );
  BUFTD16 \Nuf[1]  ( .I(n2), .OE(QEna[1]), .Z(DBusBuf[1]) );
  BUFTD16 \Nuf[0]  ( .I(n1), .OE(QEna[0]), .Z(DBusBuf[0]) );
endmodule


module DFFa_6 ( Q, D, Clr, Clk );
  input D, Clr, Clk;
  output Q;
  wire   n2;

  INVD1 U3 ( .I(Clr), .ZN(n2) );
  DFCNQD1 QReg_reg ( .D(D), .CP(Clk), .CDN(n2), .Q(Q) );
endmodule


module DFFa_5 ( Q, D, Clr, Clk );
  input D, Clr, Clk;
  output Q;
  wire   n2;

  INVD1 U3 ( .I(Clr), .ZN(n2) );
  DFCNQD1 QReg_reg ( .D(D), .CP(Clk), .CDN(n2), .Q(Q) );
endmodule


module DFFa_4 ( Q, D, Clr, Clk );
  input D, Clr, Clk;
  output Q;
  wire   n2;

  INVD1 U3 ( .I(Clr), .ZN(n2) );
  DFCNQD1 QReg_reg ( .D(D), .CP(Clk), .CDN(n2), .Q(Q) );
endmodule


module DFFa_3 ( Q, D, Clr, Clk );
  input D, Clr, Clk;
  output Q;
  wire   n2;

  INVD1 U3 ( .I(Clr), .ZN(n2) );
  DFCNQD1 QReg_reg ( .D(D), .CP(Clk), .CDN(n2), .Q(Q) );
endmodule


module DFFa_2 ( Q, D, Clr, Clk );
  input D, Clr, Clk;
  output Q;
  wire   n2;

  INVD1 U3 ( .I(Clr), .ZN(n2) );
  DFCNQD1 QReg_reg ( .D(D), .CP(Clk), .CDN(n2), .Q(Q) );
endmodule


module DFFa_1 ( Q, D, Clr, Clk );
  input D, Clr, Clk;
  output Q;
  wire   n2;

  INVD1 U3 ( .I(Clr), .ZN(n2) );
  DFCNQD1 QReg_reg ( .D(D), .CP(Clk), .CDN(n2), .Q(Q) );
endmodule


module DFFa_0 ( Q, D, Clr, Clk );
  input D, Clr, Clk;
  output Q;
  wire   n2;

  INVD1 U3 ( .I(Clr), .ZN(n2) );
  DFCNQD1 QReg_reg ( .D(D), .CP(Clk), .CDN(n2), .Q(Q) );
endmodule


module DFFa_7 ( Q, D, Clr, Clk );
  input D, Clr, Clk;
  output Q;
  wire   n1;

  INVD1 U3 ( .I(Clr), .ZN(n1) );
  DFCNQD1 QReg_reg ( .D(D), .CP(Clk), .CDN(n1), .Q(Q) );
endmodule

