// ===========================================================
// DFF:  A flip-flop with asynchronous clear, copied from
// DFFC.v to rename the module to DFF; this permits simulation
// of netlists synthesized both from the synchronous and the 
// Step 1 ripple counters without creating a name conflict.
//
// Inherits simulation `timescale.
// ------------------------------------------------------------
// 2009-02-09 jmw: v. 1.0  Copied fron DFFC and just renamed.
// ============================================================
//
module DFF (output Q, Qn, input D, Clk, Clr);
  //
  reg  QReg;  // Storage.
  //
  assign #3 Q  =  QReg; // Timing for Lab08.
  assign #3 Qn = ~QReg;
  //
  always@(posedge Clk, posedge Clr)
     if (Clr == 1'b1)
          QReg <= 1'b0;
     else QReg <= D;
  //
endmodule // DFF.
