// ===================================================
// Decoder1024Procedural.v.   Shows use of a simple for
// loop to create a 10-to-1024 decoder in RTL.
//
// Based on a Supplementary Note to Week 6 Class 2.
//
// ---------------------------------------------------
// 2010-04-21 jmw:  v. 1.0 implemented.
// ===================================================
`timescale 1ns/100ps
//
module Decoder1024Procedural
       #(parameter
          AdrHi   = 9 // default = 10-bit address bus.
        , NumAddr = (1<<AdrHi+1) - 1   // Not Silos.
        )
        (
          output[NumAddr:0] AdrEna     // VCS only.
        ,  input[AdrHi:0]   Address
        );
//
reg[NumAddr:0] AdrEnar;
assign #1 AdrEna = AdrEnar;
//
always@(Address)
  begin
  AdrEnar = 'b0;
  AdrEnar[Address] = 1'b1;
  end
//
endmodule // Decoder1024Procedural.
//
// --------------
`ifdef DC
`else
// -------------------------------------------
module Decoder1024ProceduralTst; //Same as Decoder1024Tst.
// -------------------------------------------
//
localparam AdrHi = 9;
localparam NumAddr = (1<<AdrHi+1) - 1;
//
 reg[AdrHi:0] AddrStim;
wire[NumAddr:0] AdrEnaWatch;
reg ClkStim;
//
always@(ClkStim) #50 ClkStim <= ~ClkStim;
always@(posedge ClkStim)
       begin
       #4 AddrStim = (AddrStim + 1) %NumAddr;
       #4 AddrStim = (AddrStim + 9) %NumAddr;
       #4 AddrStim = (AddrStim + 89)%NumAddr;
       #4 AddrStim = (AddrStim + 1) %NumAddr;
       end
//
initial
  begin
  #0    ClkStim  = 1'b0;
  #0    AddrStim =  'b0;
  #1000 $finish;
  end
//
Decoder1024Procedural #( .AdrHi(AdrHi) ) UTop
   (
     .AdrEna(AdrEnaWatch)
   , .Address(AddrStim)
   );
//
endmodule // Decoder1024Tst.
`endif
