# Begin_DVE_Session_Save_Info
# DVE full session
# Saved on Wed Feb 25 11:33:28 2009
# Designs open: 1
#   Sim: /home/faculty/jmw/Verilog/12Week/Setup/Home/Lab26/Lab26_Ans/FullDup_Step7/simv
# Toplevel windows open: 2
# 	TopLevel.1
# 	TopLevel.2
#   Source.1: FullDupTst
#   Wave.1: 1963 signals
#   Group count = 2
#   Group FullDupTst signal count = 15
#   Group FD_U1 signal count = 1949
# End_DVE_Session_Save_Info

# DVE version: B-2008.12
# DVE build date: Nov 16 2008 21:11:19


#<Session mode="Full" path="/home/faculty/jmw/Verilog/12Week/Setup/Home/Lab26/Lab26_Ans/FullDup_Step7/session_FullDupNetlist_FlatSDF.tcl" type="Debug">

gui_set_loading_session_type Post
gui_continuetime_set

# Close design
if { [gui_sim_state -check active] } {
    gui_sim_terminate
    gui_sim_wait terminated
}
gui_close_db -all
gui_expr_clear_all

# Close all windows
gui_close_window -type Console
gui_close_window -type Wave
gui_close_window -type Source
gui_close_window -type Schematic
gui_close_window -type Data
gui_close_window -type DriverLoad
gui_close_window -type List
gui_close_window -type Memory
gui_close_window -type HSPane
gui_close_window -type DLPane
gui_close_window -type Assertion
gui_close_window -type CovHier
gui_close_window -type CoverageTable
gui_close_window -type CoverageMap
gui_close_window -type CovDensity
gui_close_window -type CovDetail
gui_close_window -type Local
gui_close_window -type Watch
gui_close_window -type Grading
gui_close_window -type Group



# Application preferences
gui_set_pref_value -key app_default_font -value {Helvetica,9,-1,5,50,0,0,0,0,0}
gui_src_preferences -tabstop 8 -maxbits 24 -windownumber 1
#<WindowLayout>

# DVE Topleve session: 


# Create and position top-level windows :TopLevel.1

if {![gui_exist_window -window TopLevel.1]} {
    set TopLevel.1 [ gui_create_window -type TopLevel \
       -icon $::env(DVE)/auxx/gui/images/toolbars/dvewin.xpm] 
} else { 
    set TopLevel.1 TopLevel.1
}
gui_show_window -window ${TopLevel.1} -show_state normal -rect {{190 35} {1160 481}}

# ToolBar settings
gui_set_toolbar_attributes -toolbar {TimeOperations} -dock_state top
gui_set_toolbar_attributes -toolbar {TimeOperations} -offset 0
gui_show_toolbar -toolbar {TimeOperations}
gui_set_toolbar_attributes -toolbar {&File} -dock_state top
gui_set_toolbar_attributes -toolbar {&File} -offset 0
gui_show_toolbar -toolbar {&File}
gui_set_toolbar_attributes -toolbar {&Edit} -dock_state top
gui_set_toolbar_attributes -toolbar {&Edit} -offset 0
gui_show_toolbar -toolbar {&Edit}
gui_set_toolbar_attributes -toolbar {Simulator} -dock_state top
gui_set_toolbar_attributes -toolbar {Simulator} -offset 0
gui_show_toolbar -toolbar {Simulator}
gui_set_toolbar_attributes -toolbar {Signal} -dock_state top
gui_set_toolbar_attributes -toolbar {Signal} -offset 0
gui_show_toolbar -toolbar {Signal}
gui_set_toolbar_attributes -toolbar {&Scope} -dock_state top
gui_set_toolbar_attributes -toolbar {&Scope} -offset 0
gui_show_toolbar -toolbar {&Scope}
gui_set_toolbar_attributes -toolbar {&Trace} -dock_state top
gui_set_toolbar_attributes -toolbar {&Trace} -offset 0
gui_show_toolbar -toolbar {&Trace}
gui_set_toolbar_attributes -toolbar {&Window} -dock_state top
gui_set_toolbar_attributes -toolbar {&Window} -offset 0
gui_show_toolbar -toolbar {&Window}
gui_set_toolbar_attributes -toolbar {Zoom} -dock_state top
gui_set_toolbar_attributes -toolbar {Zoom} -offset 0
gui_show_toolbar -toolbar {Zoom}
gui_set_toolbar_attributes -toolbar {Zoom And Pan History} -dock_state top
gui_set_toolbar_attributes -toolbar {Zoom And Pan History} -offset 0
gui_show_toolbar -toolbar {Zoom And Pan History}

# End ToolBar settings

# Docked window settings
set HSPane.1 [gui_create_window -type HSPane -parent ${TopLevel.1} -dock_state left -dock_on_new_line true -dock_extent 321]
set Hier.1 [gui_share_window -id ${HSPane.1} -type Hier]
gui_set_window_pref_key -window ${HSPane.1} -key dock_width -value_type integer -value 321
gui_set_window_pref_key -window ${HSPane.1} -key dock_height -value_type integer -value 263
gui_set_window_pref_key -window ${HSPane.1} -key dock_offset -value_type integer -value 0
gui_update_layout -id ${HSPane.1} {{left 0} {top 0} {width 320} {height 223} {show_state normal} {dock_state left} {dock_on_new_line true} {child_hier_colhier 246} {child_hier_coltype 93} {child_hier_col1 0} {child_hier_col2 1}}
set Console.1 [gui_create_window -type Console -parent ${TopLevel.1} -dock_state bottom -dock_on_new_line true -dock_extent 105]
gui_set_window_pref_key -window ${Console.1} -key dock_width -value_type integer -value 972
gui_set_window_pref_key -window ${Console.1} -key dock_height -value_type integer -value 105
gui_set_window_pref_key -window ${Console.1} -key dock_offset -value_type integer -value 0
gui_update_layout -id ${Console.1} {{left 0} {top 0} {width 970} {height 105} {show_state normal} {dock_state bottom} {dock_on_new_line true}}
#### Start - Readjusting docked view's offset / size
set dockAreaList { top left right bottom }
foreach dockArea $dockAreaList {
  set viewList [gui_ekki_get_window_ids -active_parent -dock_area $dockArea]
  foreach view $viewList {
      if {[lsearch -exact [gui_get_window_pref_keys -window $view] dock_width] != -1} {
        set dockWidth [gui_get_window_pref_value -window $view -key dock_width]
        set dockHeight [gui_get_window_pref_value -window $view -key dock_height]
        set offset [gui_get_window_pref_value -window $view -key dock_offset]
        if { [string equal "top" $dockArea] || [string equal "bottom" $dockArea]} {
          gui_set_window_attributes -window $view -dock_offset $offset -width $dockWidth
        } else {
          gui_set_window_attributes -window $view -dock_offset $offset -height $dockHeight
        }
      }
  }
}
#### End - Readjusting docked view's offset / size
gui_sync_global -id ${TopLevel.1} -option true

# MDI window settings
set DLPane.1 [gui_create_window -type {DLPane}  -parent ${TopLevel.1}]
if {[gui_get_shared_view -id ${DLPane.1} -type Data] == {}} {
        set Data.1 [gui_share_window -id ${DLPane.1} -type Data]
} else {
        set Data.1  [gui_get_shared_view -id ${DLPane.1} -type Data]
}

gui_show_window -window ${DLPane.1} -show_state maximized
gui_update_layout -id ${DLPane.1} {{show_state maximized} {dock_state undocked} {dock_on_new_line false} {child_data_colvariable 91} {child_data_colvalue 27} {child_data_coltype 37} {child_data_col1 0} {child_data_col2 1} {child_data_col3 2} {dataShowMode detail} {max_item_length 100}}
set Source.1 [gui_create_window -type {Source}  -parent ${TopLevel.1}]
gui_show_window -window ${Source.1} -show_state maximized
gui_update_layout -id ${Source.1} {{show_state maximized} {dock_state undocked} {dock_on_new_line false}}
gui_set_active_window -window ${Source.1}

# End MDI window settings
gui_set_active_window -window ${HSPane.1}


# Create and position top-level windows :TopLevel.2

if {![gui_exist_window -window TopLevel.2]} {
    set TopLevel.2 [ gui_create_window -type TopLevel \
       -icon $::env(DVE)/auxx/gui/images/toolbars/dvewin.xpm] 
} else { 
    set TopLevel.2 TopLevel.2
}
gui_show_window -window ${TopLevel.2} -show_state normal -rect {{53 96} {1240 909}}

# ToolBar settings
gui_set_toolbar_attributes -toolbar {TimeOperations} -dock_state top
gui_set_toolbar_attributes -toolbar {TimeOperations} -offset 0
gui_show_toolbar -toolbar {TimeOperations}
gui_set_toolbar_attributes -toolbar {&File} -dock_state top
gui_set_toolbar_attributes -toolbar {&File} -offset 0
gui_show_toolbar -toolbar {&File}
gui_set_toolbar_attributes -toolbar {&Edit} -dock_state top
gui_set_toolbar_attributes -toolbar {&Edit} -offset 0
gui_show_toolbar -toolbar {&Edit}
gui_set_toolbar_attributes -toolbar {Simulator} -dock_state top
gui_set_toolbar_attributes -toolbar {Simulator} -offset 0
gui_show_toolbar -toolbar {Simulator}
gui_set_toolbar_attributes -toolbar {Signal} -dock_state top
gui_set_toolbar_attributes -toolbar {Signal} -offset 0
gui_show_toolbar -toolbar {Signal}
gui_set_toolbar_attributes -toolbar {&Scope} -dock_state top
gui_set_toolbar_attributes -toolbar {&Scope} -offset 0
gui_show_toolbar -toolbar {&Scope}
gui_set_toolbar_attributes -toolbar {&Trace} -dock_state top
gui_set_toolbar_attributes -toolbar {&Trace} -offset 0
gui_show_toolbar -toolbar {&Trace}
gui_set_toolbar_attributes -toolbar {&Window} -dock_state top
gui_set_toolbar_attributes -toolbar {&Window} -offset 0
gui_show_toolbar -toolbar {&Window}
gui_set_toolbar_attributes -toolbar {Zoom} -dock_state top
gui_set_toolbar_attributes -toolbar {Zoom} -offset 0
gui_show_toolbar -toolbar {Zoom}
gui_set_toolbar_attributes -toolbar {Zoom And Pan History} -dock_state top
gui_set_toolbar_attributes -toolbar {Zoom And Pan History} -offset 0
gui_show_toolbar -toolbar {Zoom And Pan History}

# End ToolBar settings

# Docked window settings
gui_sync_global -id ${TopLevel.2} -option true

# MDI window settings
set Wave.1 [gui_create_window -type {Wave}  -parent ${TopLevel.2}]
gui_show_window -window ${Wave.1} -show_state maximized
gui_update_layout -id ${Wave.1} {{show_state maximized} {dock_state undocked} {dock_on_new_line false} {child_wave_left 600} {child_wave_right 582} {child_wave_colname 449} {child_wave_colvalue 149} {child_wave_col1 0} {child_wave_col2 1}}
gui_set_active_window -window ${Wave.1}

# End MDI window settings
gui_set_active_window -window ${Wave.1}

gui_set_env TOPLEVELS::TARGET_FRAME(Source) ${TopLevel.1}
gui_set_env TOPLEVELS::TARGET_FRAME(Schematic) ${TopLevel.1}
gui_set_env TOPLEVELS::TARGET_FRAME(PathSchematic) ${TopLevel.1}
gui_set_env TOPLEVELS::TARGET_FRAME(Wave) none
gui_set_env TOPLEVELS::TARGET_FRAME(List) ${TopLevel.1}
gui_set_env TOPLEVELS::TARGET_FRAME(Memory) ${TopLevel.1}
gui_set_env TOPLEVELS::TARGET_FRAME(DriverLoad) none
gui_update_statusbar_target_frame ${TopLevel.1}
gui_update_statusbar_target_frame ${TopLevel.2}
# Restore toplevel window zorder
gui_set_active_window -window ${TopLevel.1}
gui_set_active_window -window ${TopLevel.2}

#</WindowLayout>

#<Database>

# DVE Open design session: 

gui_set_env SIMSETUP::SIMARGS {{-ucligui  +v2k +pathpulse +charge_decay}}
gui_set_env SIMSETUP::SIMEXE {/home/faculty/jmw/Verilog/12Week/Setup/Home/Lab26/Lab26_Ans/FullDup_Step7/simv}
gui_set_env SIMSETUP::ALLOW_POLL {0}
if { ![gui_is_db_opened -db {/home/faculty/jmw/Verilog/12Week/Setup/Home/Lab26/Lab26_Ans/FullDup_Step7/simv}] } {
gui_sim_run Ucli -exe simv -args {-ucligui  +v2k +pathpulse +charge_decay} -dir /home/faculty/jmw/Verilog/12Week/Setup/Home/Lab26/Lab26_Ans/FullDup_Step7 -nosource
}
if { ![gui_sim_state -check active] } {error "Simulator did not start correctly" error}
gui_set_precision 1ps
gui_set_time_units 1ns
#</Database>

# DVE Global setting session: 


# Global: Breakpoints

# Global: Bus

# Global: Expressions

# Global: Signal Time Shift

# Global: Signal Compare

# Global: Signal Groups
set {FullDupTst} {FullDupTst}
gui_sg_create ${FullDupTst}
gui_sg_addsignal -group ${FullDupTst} { {FullDupTst.ClockAStim} {FullDupTst.ClockBStim} {FullDupTst.CounterA} {FullDupTst.CounterB} {FullDupTst.DirectionA} {FullDupTst.DirectionB} {FullDupTst.InParDataAStim} {FullDupTst.InParDataBStim} {FullDupTst.OutParDataAWatch} {FullDupTst.OutParDataBWatch} {FullDupTst.ParValidAStim} {FullDupTst.ParValidBStim} {FullDupTst.ResetStim} {FullDupTst.RxOK_AWatch} {FullDupTst.RxOK_BWatch} }
set {FD_U1} {FD_U1}
gui_sg_create ${FD_U1}
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\*Logic1* } {FullDupTst.FD_U1.Reset} {FullDupTst.FD_U1.InParValidA} {FullDupTst.FD_U1.InParDataA} {FullDupTst.FD_U1.SerLine1} {FullDupTst.FD_U1.OutParDataA} }
gui_sg_addsignal -group ${FD_U1} { {Divider} } -divider
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.InParValidB} {FullDupTst.FD_U1.InParDataB} {FullDupTst.FD_U1.SerLine2} {FullDupTst.FD_U1.OutParDataB} {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DecodeToFIFO } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DecoderParClk } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/Count32[0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/Count32[1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/Count32[2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/Count32[3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/Count32[4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/Decoder } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[32] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[33] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[34] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[35] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[36] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[37] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[38] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[39] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[40] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[41] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[42] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[43] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[44] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[45] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[46] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[47] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[48] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[49] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[50] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[51] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[52] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[53] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[54] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[55] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[56] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[57] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[58] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[59] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[60] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[61] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[62] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/FrameSR[63] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/ParValidTimer[1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/ParValidTimer[2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/ParValidTimer[3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/UnLoad } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/DesDec_Rx1/doParSync } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/ClockW } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/DataOr } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][11] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][3] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][27] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][19] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][11] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[8][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[9][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][3] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[10][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][26] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[11][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[12][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][17] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[13][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][8] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[14][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][6] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][7] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][8] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][9] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][10] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][11] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][12] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][13] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][14] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][15] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][16] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][17] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][18] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][19] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][20] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][21] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][22] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][23] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][24] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][25] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][26] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][27] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][28] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][29] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][30] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[15][31] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_SM1/NextState } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_SM1/OldReadAr } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_SM1/OldWriteAr } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_SM1/StateClock } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/FIFO_SM1/StateClockRaw } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/SM_MemWriteCmd } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/SM_ReadAddr } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/FIFO_Rx1/SM_WriteAddr } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/ParValidDecode } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRxToDecode } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/AdjFreq } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/Comp1/ClockInN[0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/Comp1/ClockInN[1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/Comp1/CounterClockN[0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/Comp1/CounterClockN[1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/CtrCarry } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/MCntr1/Ctr } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/SampleWire } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastClock } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[1] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[0] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[1] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[2] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[3] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[4] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[5] } {FullDupTst.FD_U1.\SerDes_U1/Des_U1/SerialClk } {FullDupTst.FD_U1.\SerDes_U1/Rx_F_Empty } {FullDupTst.FD_U1.\SerDes_U1/Rx_F_Full } {FullDupTst.FD_U1.\SerDes_U1/SerLineValid } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/EncD_ToTx } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Out } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/ClockW } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/DataOr } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][6] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][7] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][8] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][9] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][10] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][11] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][12] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][13] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][14] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][15] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][16] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][17] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][18] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][19] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][20] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][21] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][22] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][23] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][24] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][25] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][26] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][27] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][28] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][29] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][30] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][31] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][6] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][7] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][8] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][9] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][10] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][11] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][12] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][13] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][14] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][15] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][16] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][17] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][18] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][19] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][20] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][21] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][22] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][23] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][24] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][25] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][26] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][27] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][28] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][29] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][30] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][31] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][6] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][7] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][8] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][9] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][10] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][11] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][12] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][13] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][14] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][15] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][16] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][17] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][18] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][19] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][20] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][21] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][22] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][23] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][24] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][25] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][26] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][27] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][28] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][29] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][30] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][31] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][6] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][7] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][8] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][9] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][10] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][11] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][12] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][13] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][14] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][15] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][16] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][17] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][18] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][19] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][20] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][21] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][22] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][23] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][24] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][25] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][26] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][27] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][28] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][29] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][30] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][31] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][6] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][7] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][8] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][9] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][10] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][11] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][12] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][13] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][14] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][15] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][16] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][17] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][18] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][19] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][20] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][21] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][22] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][23] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][24] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][25] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][26] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][27] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][28] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][29] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][30] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][31] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][6] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][7] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][8] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][9] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][10] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][11] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][12] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][13] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][14] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][15] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][16] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][17] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][18] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][19] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][20] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][21] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][22] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][23] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][24] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][25] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][26] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][27] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][28] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][29] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][30] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][31] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][6] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][7] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][8] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][9] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][10] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][11] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][12] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][13] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][14] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][15] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][16] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][17] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][18] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][19] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][20] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][21] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][22] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][23] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][24] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][25] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][26] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][27] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][28] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][29] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][30] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][31] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][6] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][7] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][8] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][9] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][10] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][11] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][12] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][13] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][14] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][15] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][16] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][17] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][18] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][19] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][20] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][21] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][22] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][23] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][24] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][25] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][26] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][27] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][28] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][29] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][30] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][31] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/CurState[0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/CurState[1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/CurState[2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/NextState[0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/NextState[1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/NextState[2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/OldReadAr[0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/OldReadAr[1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/OldReadAr[2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/OldWriteAr[0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/OldWriteAr[1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/OldWriteAr[2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/StateClock } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/FIFO_SM1/StateClockRaw } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/SM_MemWriteCmd } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/SM_ReadAddr } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/FIFO_Tx1/SM_WriteAddr } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/F_ReadReq } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/F_Valid } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/F_WriteReq } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerClk } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerEnc_Tx1/HalfParClkr } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerEnc_Tx1/InBuf } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerEnc_Tx1/Sh_N[0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerEnc_Tx1/Sh_N[1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerEnc_Tx1/Sh_N[2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerEnc_Tx1/Sh_N[3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerEnc_Tx1/Sh_N[4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerEnc_Tx1/Sh_N[5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/AdjFreq } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/Comp1/ClockInN[0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/Comp1/ClockInN[1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/Comp1/CounterClockN[0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/Comp1/CounterClockN[1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/Comp1/ZeroCounters } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/CtrCarry } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/MCntr1/Ctr } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/SampleWire } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastClock } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[5] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[0] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[1] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[2] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[3] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[4] } {FullDupTst.FD_U1.\SerDes_U1/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[5] } {FullDupTst.FD_U1.\SerDes_U1/Tx_F_Empty } {FullDupTst.FD_U1.\SerDes_U1/Tx_F_Full } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DecodeToFIFO } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DecoderParClk } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Count32[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Count32[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Count32[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Count32[3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Count32[4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[6] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[7] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[8] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[9] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[10] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[11] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[12] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[13] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[14] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[15] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[16] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[17] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[18] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[19] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[20] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[21] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[22] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[23] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[24] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[25] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[26] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[27] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[28] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[29] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[30] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/Decoder[31] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[6] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[7] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[8] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[9] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[10] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[11] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[12] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[13] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[14] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[15] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[16] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[17] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[18] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[19] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[20] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[21] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[22] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[23] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[24] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[25] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[26] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[27] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[28] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[29] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[30] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[31] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[32] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[33] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[34] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[35] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[36] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[37] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[38] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[39] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[40] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[41] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[42] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[43] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[44] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[45] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[46] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[47] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[48] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[49] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[50] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[51] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[52] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[53] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[54] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[55] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[56] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[57] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[58] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[59] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[60] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[61] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[62] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/FrameSR[63] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/ParValidTimer[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/ParValidTimer[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/ParValidTimer[3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/UnLoad } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/DesDec_Rx1/doParSync } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/ClockW } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/DataOr } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][6] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][7] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][8] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][9] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][10] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][11] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][12] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][13] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][14] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][15] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][16] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][17] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][18] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][19] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][20] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][21] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][22] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][23] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][24] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][25] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][26] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][27] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][28] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][29] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][30] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[0][31] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][3] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][6] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][7] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][8] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][9] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][10] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][11] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][12] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][13] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][14] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][15] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][16] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][17] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][18] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][19] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][20] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][21] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][22] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][23] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][24] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][25] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][26] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][27] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][28] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][29] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][30] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[1][31] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][6] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][7] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][8] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][9] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][10] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][11] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][12] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][13] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][14] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][15] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][16] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][17] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][18] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][19] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][20] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][21] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][22] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][23] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][24] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][25] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][26] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][27] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][28] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][29] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][30] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[2][31] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][6] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][7] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][8] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][9] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][10] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][11] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][12] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][13] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][14] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][15] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][16] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][17] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][18] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][19] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][20] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][21] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][22] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][23] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][24] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][25] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][26] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][27] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][28] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][29] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][30] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[3][31] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][6] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][7] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][8] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][9] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][10] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][11] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][12] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][13] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][14] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][15] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][16] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][17] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][18] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][19] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][20] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][21] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][22] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][23] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][24] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][25] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][26] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][27] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][28] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][29] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][30] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[4][31] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][6] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][7] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][8] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][9] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][10] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][11] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][12] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][13] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][14] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][15] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][16] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][17] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][18] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][19] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][20] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][21] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][22] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][23] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][24] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][25] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][26] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][27] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][28] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][29] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][30] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[5][31] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][6] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][7] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][8] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][9] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][10] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][11] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][12] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][13] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][14] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][15] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][16] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][17] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][18] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][19] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][20] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][21] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][22] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][23] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][24] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][25] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][26] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][27] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][28] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][29] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][30] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[6][31] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][6] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][7] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][8] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][9] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][10] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][11] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][12] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][13] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][14] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][15] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][16] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][17] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][18] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][19] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][20] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][21] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][22] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][23] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][24] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][25] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][26] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][27] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][28] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][29] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][30] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_Mem1/Storage[7][31] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/CurState[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/CurState[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/CurState[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/NextState[0] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/NextState[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/NextState[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/OldReadAr[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/OldReadAr[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/OldReadAr[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/OldWriteAr[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/OldWriteAr[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/OldWriteAr[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/StateClock } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/FIFO_SM1/StateClockRaw } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/SM_MemWriteCmd } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/SM_ReadAddr } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/SM_WriteAddr } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/FIFO_Rx1/n4 } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/ParValidDecode } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRxToDecode } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/AdjFreq } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/Comp1/ClockInN[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/Comp1/ClockInN[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/Comp1/CounterClockN[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/Comp1/CounterClockN[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/CtrCarry } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/MCntr1/Ctr } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/SampleWire } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DP_OP_18_301_681/n2 } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DP_OP_18_301_681/n3 } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DP_OP_18_301_681/n4 } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DP_OP_18_301_681/n5 } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/DivideFactor[5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastClock } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/FastDivvy[5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[0] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[1] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[2] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[3] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[4] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerRx_Rx1/PLL_RxU1/VFO1/WireD[5] } {FullDupTst.FD_U1.\SerDes_U2/Des_U1/SerialClk } {FullDupTst.FD_U1.\SerDes_U2/Rx_F_Empty } {FullDupTst.FD_U1.\SerDes_U2/Rx_F_Full } {FullDupTst.FD_U1.\SerDes_U2/SerLineValid } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/EncD_ToTx } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Out } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/ClockW } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/DataOr } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][3] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[0][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][27] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[1][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[2][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][19] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[3][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[4][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][11] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[5][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[6][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][3] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[7][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][27] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[8][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[9][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][19] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[10][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[11][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][10] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[12][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[13][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][1] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][24] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[14][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][6] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][7] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][8] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][9] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][10] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][11] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][12] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][13] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][14] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][15] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][16] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][17] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][18] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][19] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][20] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][21] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][22] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][23] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][24] } }
gui_sg_addsignal -group ${FD_U1} { {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][25] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][26] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][27] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][28] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][29] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][30] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_Mem1/Storage[15][31] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_SM1/NextState } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_SM1/OldReadAr } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_SM1/OldWriteAr } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_SM1/StateClock } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/FIFO_SM1/StateClockRaw } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/SM_MemWriteCmd } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/SM_ReadAddr } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/FIFO_Tx1/SM_WriteAddr } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/F_ReadReq } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/F_Valid } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/F_WriteReq } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerClk } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerEnc_Tx1/HalfParClkr } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerEnc_Tx1/InBuf } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerEnc_Tx1/Sh_N[0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerEnc_Tx1/Sh_N[1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerEnc_Tx1/Sh_N[2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerEnc_Tx1/Sh_N[3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerEnc_Tx1/Sh_N[4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerEnc_Tx1/Sh_N[5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/AdjFreq } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/Comp1/ClockInN[0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/Comp1/ClockInN[1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/Comp1/CounterClockN[0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/Comp1/CounterClockN[1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/Comp1/ZeroCounters } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/CtrCarry } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/MCntr1/Ctr } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/SampleWire } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/DivideFactor[5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastClock } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/FastDivvy[5] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[0] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[1] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[2] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[3] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[4] } {FullDupTst.FD_U1.\SerDes_U2/Ser_U1/SerTx_Tx1/PLL_TxU1/VFO1/WireD[5] } {FullDupTst.FD_U1.\SerDes_U2/Tx_F_Empty } {FullDupTst.FD_U1.\SerDes_U2/Tx_F_Full } }

# Global: Highlighting

# Post database loading setting...

# Restore C1 time
gui_set_time -C1_only 308031



# Save global setting...

# Wave/List view global setting
gui_cov_show_value -switch false

# Close all empty TopLevel windows
foreach __top [gui_ekki_get_window_ids -type TopLevel] {
    if { [llength [gui_ekki_get_window_ids -parent $__top]] == 0} {
        gui_close_window -window $__top
    }
}
gui_set_loading_session_type noSession
# DVE View/pane content session: 


# Hier 'Hier.1'
gui_list_set_filter -id ${Hier.1} -list { {Package 1} {All 1} {Process 1} {UnnamedProcess 1} {Assertion 1} {Function 1} {Block 1} {LeafScCell 1} {LeafVlgCell 1} {Interface 1} {LeafVhdCell 1} {NamedBlock 1} {Task 1} {DollarUnit 1} {VlgPackage 1} {ClassDef 1} }
gui_list_set_filter -id ${Hier.1} -text {*}
gui_hier_list_init -id ${Hier.1}
gui_change_design -id ${Hier.1} -design Sim
catch {gui_list_expand -id ${Hier.1} FullDupTst}
catch {gui_list_select -id ${Hier.1} {FullDupTst.FD_U1}}
gui_view_scroll -id ${Hier.1} -vertical -set 0
gui_view_scroll -id ${Hier.1} -horizontal -set 0

# Data 'Data.1'
gui_list_set_filter -id ${Data.1} -list { {Buffer 1} {Input 1} {Others 1} {Linkage 1} {Output 1} {Parameter 1} {All 1} {Aggregate 1} {Event 1} {Assertion 1} {Constant 1} {Signal 1} {$unit 1} {Inout 1} {Variable 1} }
gui_list_set_filter -id ${Data.1} -text {*}
gui_list_show_data -id ${Data.1} {FullDupTst.FD_U1}
gui_view_scroll -id ${Data.1} -vertical -set 0
gui_view_scroll -id ${Data.1} -horizontal -set 0
gui_view_scroll -id ${Hier.1} -vertical -set 0
gui_view_scroll -id ${Hier.1} -horizontal -set 0

# Source 'Source.1'
gui_src_value_annotate -id ${Source.1} -switch false
gui_set_env TOGGLE::VALUEANNOTATE 0
gui_open_source -id ${Source.1}  -replace -active FullDupTst /home/faculty/jmw/Verilog/12Week/Setup/Home/Lab26/Lab26_Ans/FullDup_Step7/FullDupTst.v
gui_view_scroll -id ${Source.1} -vertical -set 104
gui_src_set_reusable -id ${Source.1}

# View 'Wave.1'
gui_wv_sync -id ${Wave.1} -switch false
set groupExD [gui_get_pref_value -category Wave -key exclusiveSG]
gui_set_pref_value -category Wave -key exclusiveSG -value {false}
set origWaveHeight [gui_get_pref_value -category Wave -key waveRowHeight]
gui_list_set_height -id Wave -height 25
set origGroupCreationState [gui_list_create_group_when_add -wave]
gui_list_create_group_when_add -wave -disable
gui_marker_set_ref -id ${Wave.1}  C1
gui_wv_zoom_timerange -id ${Wave.1} 0 211371.7
gui_list_set_filter -id ${Wave.1} -list { {Buffer 1} {Input 1} {Others 1} {Linkage 1} {Output 1} {Parameter 1} {All 1} {Aggregate 1} {Event 1} {Assertion 1} {Constant 1} {Signal 1} {$unit 1} {Inout 1} {Variable 1} }
gui_list_set_filter -id ${Wave.1} -text {*}
gui_list_add_group -id ${Wave.1} -after {New Group} {{FullDupTst}}
gui_list_add_group -id ${Wave.1} -after {New Group} {{FD_U1}}
gui_list_collapse -id ${Wave.1} {FullDupTst}
gui_list_select -id ${Wave.1} {FullDupTst.FD_U1.Reset }
gui_list_set_insertion_bar  -id ${Wave.1} -group {FD_U1} -item FullDupTst.FD_U1.Reset -position below
gui_seek_criteria -id ${Wave.1} {Any Edge}



gui_set_env TOGGLE::DEFAULT_WAVE_WINDOW ${Wave.1}
gui_set_pref_value -category Wave -key exclusiveSG -value $groupExD
gui_list_set_height -id Wave -height $origWaveHeight
if {$origGroupCreationState} {
	gui_list_create_group_when_add -wave -enable
}
if { $groupExD } {
 gui_msg_report -code DVWW028 
}
gui_marker_move -id ${Wave.1} {C1} 308031
gui_view_scroll -id ${Wave.1} -vertical -set 0
#</Session>

