
module PLLTop ( ClockOut, ClockIn, Reset );
  input ClockIn, Reset;
  output ClockOut;
  wire   n6, SampleWire, CtrCarry, n2, n3, n4, n5;
  wire   [1:0] AdjFreq;

  DEL005 SampleDelay1 ( .I(ClockIn), .Z(SampleWire) );
  ClockComparator Comp1 ( .AdjustFreq(AdjFreq), .ClockIn(ClockIn), 
        .CounterClock(CtrCarry), .Reset(n5) );
  VFO VFO1 ( .ClockOut(n6), .AdjustFreq(AdjFreq), .Sample(SampleWire), .Reset(
        n5) );
  MultiCounter MCntr1 ( .CarryOut(CtrCarry), .Clock(n4), .Reset(n5) );
  CKND16 U1 ( .CLK(n2), .CN(n3) );
  CKND16 U2 ( .CLK(n2), .CN(ClockOut) );
  CKND0 U3 ( .CLK(n6), .CN(n2) );
  BUFFD0 U4 ( .I(n3), .Z(n4) );
  BUFFD1 U5 ( .I(Reset), .Z(n5) );
endmodule


module MultiCounter ( CarryOut, Clock, Reset );
  input Clock, Reset;
  output CarryOut;
  wire   N1, N2, N3, N4, N5, \add_16/carry[4] , \add_16/carry[3] ,
         \add_16/carry[2] , n1;
  wire   [3:0] Ctr;

  DFCNQD1 \Ctr_reg[1]  ( .D(N2), .CP(Clock), .CDN(n1), .Q(Ctr[1]) );
  DFCNQD1 \Ctr_reg[2]  ( .D(N3), .CP(Clock), .CDN(n1), .Q(Ctr[2]) );
  DFCNQD1 \Ctr_reg[3]  ( .D(N4), .CP(Clock), .CDN(n1), .Q(Ctr[3]) );
  DFCNQD1 \Ctr_reg[0]  ( .D(N1), .CP(Clock), .CDN(n1), .Q(Ctr[0]) );
  DFCNQD1 \Ctr_reg[4]  ( .D(N5), .CP(Clock), .CDN(n1), .Q(CarryOut) );
  INVD1 U3 ( .I(Reset), .ZN(n1) );
  HA1D0 U4 ( .A(Ctr[2]), .B(\add_16/carry[2] ), .CO(\add_16/carry[3] ), .S(N3)
         );
  HA1D0 U5 ( .A(Ctr[1]), .B(Ctr[0]), .CO(\add_16/carry[2] ), .S(N2) );
  HA1D0 U6 ( .A(Ctr[3]), .B(\add_16/carry[3] ), .CO(\add_16/carry[4] ), .S(N4)
         );
  CKND0 U7 ( .CLK(Ctr[0]), .CN(N1) );
  CKXOR2D0 U8 ( .A1(\add_16/carry[4] ), .A2(CarryOut), .Z(N5) );
endmodule


module VFO ( ClockOut, AdjustFreq, Sample, Reset );
  input [1:0] AdjustFreq;
  input Sample, Reset;
  output ClockOut;
  wire   FastClock, N9, N10, N11, N12, N13, N14, N16, N17, N18, N19, N20, N21,
         N30, N31, N32, N33, N34, N35, N39, N40, N41, N42, N43, n13, n15, n16,
         n17, n18, n19, n20, \add_182/carry[5] , \add_182/carry[4] ,
         \add_182/carry[3] , \add_182/carry[2] , \add_163/carry[5] ,
         \add_163/carry[4] , \add_163/carry[3] , \add_163/carry[2] , n1, n2,
         n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n14, n21, n22, n23, n24,
         n25, n26, n27, n28, n29, n30, n31;
  wire   [5:0] WireD;
  wire   [5:0] FastDivvy;
  wire   [5:0] DivideFactor;

  DEL005 \DelayLine[0].Delay83ps  ( .I(WireD[0]), .Z(WireD[1]) );
  DEL005 \DelayLine[1].Delay83ps  ( .I(WireD[1]), .Z(WireD[2]) );
  DEL005 \DelayLine[2].Delay83ps  ( .I(WireD[2]), .Z(WireD[3]) );
  DEL005 \DelayLine[3].Delay83ps  ( .I(WireD[3]), .Z(WireD[4]) );
  DEL005 \DelayLine[4].Delay83ps  ( .I(WireD[4]), .Z(WireD[5]) );
  DFCNQD1 ClockOutReg_reg ( .D(n13), .CP(FastClock), .CDN(n31), .Q(ClockOut)
         );
  DFCNQD1 \FastDivvy_reg[5]  ( .D(N21), .CP(FastClock), .CDN(n31), .Q(
        FastDivvy[5]) );
  DFCNQD1 \FastDivvy_reg[2]  ( .D(N18), .CP(FastClock), .CDN(n31), .Q(
        FastDivvy[2]) );
  DFCNQD1 \FastDivvy_reg[0]  ( .D(N16), .CP(FastClock), .CDN(n31), .Q(
        FastDivvy[0]) );
  DFCNQD1 \FastDivvy_reg[1]  ( .D(N17), .CP(FastClock), .CDN(n31), .Q(
        FastDivvy[1]) );
  DFCNQD1 \FastDivvy_reg[4]  ( .D(N20), .CP(FastClock), .CDN(n31), .Q(
        FastDivvy[4]) );
  DFCNQD1 \FastDivvy_reg[3]  ( .D(N19), .CP(FastClock), .CDN(n31), .Q(
        FastDivvy[3]) );
  DFCNQD1 \DivideFactor_reg[5]  ( .D(n19), .CP(Sample), .CDN(n31), .Q(
        DivideFactor[5]) );
  DFCNQD1 \DivideFactor_reg[3]  ( .D(n16), .CP(Sample), .CDN(n31), .Q(
        DivideFactor[3]) );
  DFCNQD1 \DivideFactor_reg[2]  ( .D(n17), .CP(Sample), .CDN(n31), .Q(
        DivideFactor[2]) );
  DFSND1 \DivideFactor_reg[4]  ( .D(n15), .CP(Sample), .SDN(n31), .Q(
        DivideFactor[4]), .QN(n25) );
  DFSND1 \DivideFactor_reg[1]  ( .D(n18), .CP(Sample), .SDN(n31), .Q(
        DivideFactor[1]), .QN(n11) );
  DFSND1 \DivideFactor_reg[0]  ( .D(n20), .CP(Sample), .SDN(n31), .Q(
        DivideFactor[0]), .QN(N30) );
  INVD1 U3 ( .I(Reset), .ZN(n31) );
  OR2D1 U4 ( .A1(DivideFactor[1]), .A2(DivideFactor[0]), .Z(n1) );
  HA1D0 U5 ( .A(DivideFactor[2]), .B(\add_182/carry[2] ), .CO(
        \add_182/carry[3] ), .S(N32) );
  HA1D0 U6 ( .A(DivideFactor[3]), .B(\add_182/carry[3] ), .CO(
        \add_182/carry[4] ), .S(N33) );
  HA1D0 U7 ( .A(DivideFactor[1]), .B(DivideFactor[0]), .CO(\add_182/carry[2] ), 
        .S(N31) );
  HA1D0 U8 ( .A(DivideFactor[4]), .B(\add_182/carry[4] ), .CO(
        \add_182/carry[5] ), .S(N34) );
  HA1D0 U9 ( .A(FastDivvy[3]), .B(\add_163/carry[3] ), .CO(\add_163/carry[4] ), 
        .S(N12) );
  HA1D0 U10 ( .A(FastDivvy[1]), .B(FastDivvy[0]), .CO(\add_163/carry[2] ), .S(
        N10) );
  HA1D0 U11 ( .A(FastDivvy[2]), .B(\add_163/carry[2] ), .CO(\add_163/carry[3] ), .S(N11) );
  HA1D0 U12 ( .A(FastDivvy[4]), .B(\add_163/carry[4] ), .CO(\add_163/carry[5] ), .S(N13) );
  CKND0 U13 ( .CLK(FastDivvy[0]), .CN(N9) );
  CKXOR2D0 U14 ( .A1(\add_163/carry[5] ), .A2(FastDivvy[5]), .Z(N14) );
  CKXOR2D0 U15 ( .A1(\add_182/carry[5] ), .A2(DivideFactor[5]), .Z(N35) );
  IOA21D0 U16 ( .A1(DivideFactor[0]), .A2(DivideFactor[1]), .B(n1), .ZN(N39)
         );
  NR2D0 U17 ( .A1(n1), .A2(DivideFactor[2]), .ZN(n2) );
  AO21D0 U18 ( .A1(n1), .A2(DivideFactor[2]), .B(n2), .Z(N40) );
  CKND2D0 U19 ( .A1(n2), .A2(n12), .ZN(n3) );
  OAI21D0 U20 ( .A1(n2), .A2(n12), .B(n3), .ZN(N41) );
  XNR2D0 U21 ( .A1(n3), .A2(DivideFactor[4]), .ZN(N42) );
  NR2D0 U22 ( .A1(DivideFactor[4]), .A2(n3), .ZN(n4) );
  CKXOR2D0 U23 ( .A1(DivideFactor[5]), .A2(n4), .Z(N43) );
  AO222D0 U24 ( .A1(N30), .A2(n5), .B1(N30), .B2(n6), .C1(DivideFactor[0]), 
        .C2(n7), .Z(n20) );
  AO222D0 U25 ( .A1(N35), .A2(n5), .B1(N43), .B2(n6), .C1(DivideFactor[5]), 
        .C2(n7), .Z(n19) );
  AO222D0 U26 ( .A1(N31), .A2(n5), .B1(N39), .B2(n6), .C1(DivideFactor[1]), 
        .C2(n7), .Z(n18) );
  AO222D0 U27 ( .A1(N32), .A2(n5), .B1(N40), .B2(n6), .C1(DivideFactor[2]), 
        .C2(n7), .Z(n17) );
  AO222D0 U28 ( .A1(N33), .A2(n5), .B1(N41), .B2(n6), .C1(DivideFactor[3]), 
        .C2(n7), .Z(n16) );
  AO222D0 U29 ( .A1(N34), .A2(n5), .B1(N42), .B2(n6), .C1(DivideFactor[4]), 
        .C2(n7), .Z(n15) );
  INR2D0 U30 ( .A1(AdjustFreq[0]), .B1(n7), .ZN(n6) );
  NR2D0 U31 ( .A1(n7), .A2(AdjustFreq[0]), .ZN(n5) );
  MUX2D0 U32 ( .I0(n8), .I1(n9), .S(AdjustFreq[1]), .Z(n7) );
  OAI31D0 U33 ( .A1(n10), .A2(DivideFactor[5]), .A3(DivideFactor[4]), .B(
        AdjustFreq[0]), .ZN(n9) );
  AO31D0 U34 ( .A1(DivideFactor[5]), .A2(n10), .A3(DivideFactor[4]), .B(
        AdjustFreq[0]), .Z(n8) );
  INR3D0 U35 ( .A1(DivideFactor[2]), .B1(n11), .B2(n12), .ZN(n10) );
  CKXOR2D0 U36 ( .A1(ClockOut), .A2(n14), .Z(n13) );
  INR2D0 U37 ( .A1(N14), .B1(n14), .ZN(N21) );
  INR2D0 U38 ( .A1(N13), .B1(n14), .ZN(N20) );
  INR2D0 U39 ( .A1(N12), .B1(n14), .ZN(N19) );
  INR2D0 U40 ( .A1(N11), .B1(n14), .ZN(N18) );
  INR2D0 U41 ( .A1(N10), .B1(n14), .ZN(N17) );
  INR2D0 U42 ( .A1(N9), .B1(n14), .ZN(N16) );
  OA21D0 U43 ( .A1(FastDivvy[5]), .A2(n21), .B(n22), .Z(n14) );
  IOA22D0 U44 ( .B1(n23), .B2(n24), .A1(n21), .A2(FastDivvy[5]), .ZN(n22) );
  AOI221D0 U45 ( .A1(FastDivvy[4]), .A2(n25), .B1(FastDivvy[3]), .B2(n12), .C(
        n26), .ZN(n24) );
  AOI221D0 U46 ( .A1(DivideFactor[3]), .A2(n27), .B1(DivideFactor[2]), .B2(n28), .C(n29), .ZN(n26) );
  IAO21D0 U47 ( .A1(n28), .A2(DivideFactor[2]), .B(FastDivvy[2]), .ZN(n29) );
  OAI32D0 U48 ( .A1(N30), .A2(FastDivvy[0]), .A3(n30), .B1(FastDivvy[1]), .B2(
        n11), .ZN(n28) );
  AN2D0 U49 ( .A1(FastDivvy[1]), .A2(n11), .Z(n30) );
  CKND0 U50 ( .CLK(FastDivvy[3]), .CN(n27) );
  CKND0 U51 ( .CLK(DivideFactor[3]), .CN(n12) );
  NR2D0 U52 ( .A1(FastDivvy[4]), .A2(n25), .ZN(n23) );
  CKND0 U53 ( .CLK(DivideFactor[5]), .CN(n21) );
  CKND0 U54 ( .CLK(WireD[0]), .CN(FastClock) );
  CKND2D0 U55 ( .A1(WireD[5]), .A2(n31), .ZN(WireD[0]) );
endmodule


module ClockComparator ( AdjustFreq, ClockIn, CounterClock, Reset );
  output [1:0] AdjustFreq;
  input ClockIn, CounterClock, Reset;
  wire   N6, N8, N24, N25, N26, n7, n8, n9, n2, n3, n4, n5, n6;
  wire   [1:0] ClockInN;
  wire   [1:0] CounterClockN;

  MOAI22D1 U5 ( .A1(N8), .A2(n7), .B1(n8), .B2(ClockInN[1]), .ZN(N25) );
  MOAI22D1 U8 ( .A1(CounterClockN[1]), .A2(n9), .B1(n8), .B2(N26), .ZN(N24) );
  DFCNQD1 \AdjustFreq_reg[1]  ( .D(N25), .CP(CounterClock), .CDN(n6), .Q(
        AdjustFreq[1]) );
  DFSNQD1 \AdjustFreq_reg[0]  ( .D(N24), .CP(CounterClock), .SDN(n6), .Q(
        AdjustFreq[0]) );
  DFCNQD1 \CounterClockN_reg[0]  ( .D(n5), .CP(CounterClock), .CDN(n2), .Q(
        CounterClockN[0]) );
  DFCNQD1 \CounterClockN_reg[1]  ( .D(N8), .CP(CounterClock), .CDN(n2), .Q(
        CounterClockN[1]) );
  DFCNQD1 \ClockInN_reg[1]  ( .D(N6), .CP(ClockIn), .CDN(n2), .Q(ClockInN[1])
         );
  DFCNQD1 \ClockInN_reg[0]  ( .D(n3), .CP(ClockIn), .CDN(n2), .Q(ClockInN[0])
         );
  DFSND1 ZeroCounters_reg ( .D(N26), .CP(ClockIn), .SDN(n6), .QN(n2) );
  NR2D1 U3 ( .A1(n4), .A2(n3), .ZN(N26) );
  XOR2D1 U4 ( .A1(n3), .A2(n4), .Z(N6) );
  INVD1 U6 ( .I(Reset), .ZN(n6) );
  INVD1 U7 ( .I(ClockInN[0]), .ZN(n3) );
  INVD1 U9 ( .I(ClockInN[1]), .ZN(n4) );
  AOI21D1 U10 ( .A1(ClockInN[0]), .A2(n8), .B(N26), .ZN(n7) );
  NR2D1 U11 ( .A1(n5), .A2(N6), .ZN(n9) );
  ND2D1 U12 ( .A1(CounterClockN[1]), .A2(CounterClockN[0]), .ZN(n8) );
  INVD1 U13 ( .I(CounterClockN[0]), .ZN(n5) );
  XNR2D1 U14 ( .A1(n5), .A2(CounterClockN[1]), .ZN(N8) );
endmodule

